Datasheet

LM4549B
www.ti.com SNAS598A –JULY 2012–REVISED MAY 2013
resolution of 1 Hz) is supported. Slot Requests from the LM4549B are issued completely deterministically. For
example if a sample rate of 8000 Hz is programmed into 2Ch then the LM4549B will always issue a slot request
in every sixth frame. A frequency of 9600 Hz will result in a request every fifth frame while a frequency of 8800
Hz will cause slot requests to be spaced alternately five and six frames apart. This determinism makes it easy to
plan task scheduling on a system controller and simplifies application software development.
The LM4549B will ignore data in Output Frame slots that do not follow an Input Frame with a Slot Request. For
example, if the LM4549B is expecting data at a 8000 Hz rate yet the AC '97 Digital Audio Controller continues to
send data at 48000 Hz, then only those one-in-six audio samples that follow a Slot Request will be used by the
DAC. The rest will be discarded.
Bits 9 – 2 are request bits for slots not used by the LM4549B and are stuffed with zeros. Bits 1 and 0 are
reserved and are also stuffed with zeros.
Table 6. Slot 1, Input Frame
Bits Description Comment
19 Reserved Stuffed with "0" by LM4549B
18:12 Status Register Index Echo of the requested Status Register address.
0 = Controller should send valid data in Slot 3 of the next Output
Slot 3 Request bit
Frame.
11
(For left DAC PCM data)
1 = Controller should not send Slot 3 data.
0 = Controller should send valid data in Slot 4 of the next Output
Slot 4 Request bit
Frame.
10
(For right DAC PCM data)
1 = Controller should not send Slot 4 data.
9:2 Unused Slot Request bits Stuffed with "0"s by LM4549B
1,0 Reserved Stuffed with "0"s by LM4549B
SDATA_IN: Slot 2 – Status Data
This slot returns 16-bit status data read from a codec control/status register. The codec sends the data in the
frame following a read-request by the controller (bit 15, slot 1 of the Output Frame). If no read-request was made
in the previous frame the codec will stuff this slot with zeros.
Table 7. Slot 2, Input Frame
Bits Description Comment
Data read from a codec control/status register.
19:4 Status Data
Stuffed with “0”s if no read-request in previous frame.
3:0 Reserved Stuffed with "0"s by LM4549B
SDATA_IN: Slot 3 – PCM Record Left Channel
This slot contains sampled data from the left channel of the stereo ADC. The signal to be digitized is selected
using the Record Select register (1Ah) and subsequently routed through the Record Select Mux and the Record
Gain amplifier to the ADC.
This is a 20-bit slot and the digitized 18-bit PCM data is transmitted in an MSB justified format. The remaining 2
LSBs are stuffed with zeros.
Table 8. Slot 3, Input Frame
Bits Description Comment
19:2 PCM Record Left Channel data 18-bit PCM sample from left ADC
1:0 Reserved Stuffed with "0"s by LM4549B
SDATA_IN: Slot 4 – PCM Record Right Channel
This slot contains sampled data from the right channel of the stereo ADC. The signal to be digitized is selected
using the Record Select register (1Ah) and subsequently routed through the Record Select Mux and the Record
Gain amplifier to the ADC.
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