Datasheet

BIT_CLK
SDATA_IN
SYNC
LM4549B samples
SYNC assertion
LM4549B outputs
first bit of SDATA_IN
End of previous
Audio Frame
Codec
Ready
Slot
(1)
Slot
(2)
LM4549B
SNAS598A –JULY 2012–REVISED MAY 2013 www.ti.com
Figure 21. Start of AC Link Input Frame
SDATA_IN: Slot 0 – Codec/Slot Status Bits
The first bit (bit 15, “Codec Ready”) of slot 0 in the AC Link Input Frame indicates when the codec's AC Link
digital interface and its status/control registers are fully operational. The digital controller is then able to read the
LSBs from the Powerdown Control/Stat register (26h) to determine the status of the four main analog
subsections. It is important to check the status of these subsections after Initialization, Cold Reset, or the use of
the powerdown modes in order to minimize the risk of distorting analog signals passed before the subsections
are ready.
The 4 bits 14, 13, 12 and 11 indicate that the data in slots 1, 2, 3 and 4, respectively, are valid.
Table 5. Slot 0, Input Frame
Bit Description Comment
15 Codec Ready Bit 1 = AC Link Interface Ready
14 Slot 1 data valid 1 = Valid Status Address or Slot Request
13 Slot 2 data valid 1 = Valid Status Data
1 = Valid PCM Data
12 Slot 3 data valid
(Left ADC)
1 = Valid PCM Data
11 Slot 4 data valid
(Right ADC)
SDATA_IN: Slot 1 – Status Address / Slot Request Bits
This slot echoes (in bits 18 – 12) the 7-bit address of the codec control/status register received from the
controller as part of a read-request in the previous frame. If no read-request was received, the codec stuffs these
bits with zeros.
Bits 11, 10 are Slot Request bits that support the Variable Rate Audio (VRA) capabilities of the LM4549B. For all
codec Primary and Secondary modes, the left and right channels of the DAC take PCM data from slots 3 and 4
in the Output Frame respectively. The codec uses bits 11 and 10 to request DAC data from these two slots. If
bits 11 and 10 are set to 0, the controller should respond with valid PCM data in slots 3 and 4 of the next Output
Frame. If bits 11 and 10 are set to 1, the controller should not send data.
The codec has full control of the slot request bits. By default, data is requested in every frame, corresponding to
a sample rate equal to the frame rate (SYNC frequency) – 48 kHz when XTAL_IN = 24.576 MHz. To send
samples at a rate below the frame rate, a controller should set VRA = 1 (bit 0 in the Extended Audio
Control/Status register, 2Ah) and program the desired rate into the PCM DAC Rate register, 2Ch. Both DAC
channels operate at the same sample rate. Values for common sample rates are given in the Register
Descriptions section (Sample Rate Control Registers, 2Ch, 32h) but any rate between 4 kHz and 48 kHz (to a
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