Datasheet

BIT_CLK
SDATA_IN
SYNC
End of previous
Audio Frame
Codec
Ready
Slot
(1)
Slot
(4)
^0_ Bit 19 Bit 0
Bit 19
Slot 2
Bit 0
Slot 12
SLOTS 2 to 12SLOT 1
^0_
Tag bits: }ZÇv^o}š^so]_]š•
Tag Phase
20.8 Ps
(48 kHz)
Data Phase
Status Address / Slot
Request bits for VSA
Slot (x) = ³1´LQGLFDWHVWLPHVORWx contains valid PCM data
Data: Status and Audio
LM4549B
www.ti.com SNAS598A –JULY 2012–REVISED MAY 2013
SDATA_OUT: Slots 3 & 4 – PCM Playback Left/Right Channels
Slots 3 and 4 are 20-bit fields used to transmit PCM data to the left and right channels of the stereo DAC for all
codec Primary and Secondary modes. Any unused bits should be stuffed with zeros. The LM4549B DACs have
18-bit resolution and will therefore use the 18 MSBs of the 20-bit PCM data (MSB justified).
Table 4. Slots 3 & 4, Output Frame
Bits Description Comment
PCM DAC Data Slots used to stream data to DACs for all Primary or Secondary modes.
19:0
(Left /Right Channels) Set unused bits to "0"
SDATA_OUT: Slots 5 to 12 – Reserved
These slots are not used by the LM4549B and should all be stuffed with zeros by the AC '97 Controller.
Figure 20. AC Link Input Frame
AC Link Input Frame: SDATA_IN, Controller Input from LM4549B Output
The AC Link Input Frame contains status and PCM data from the LM4549B control registers and stereo ADC.
Input Frames are carried on the SDATA_IN signal which is an input to the AC '97 Digital Audio Controller and an
output from the LM4549B codec. As shown in Figure 17, Input Frames are constructed from thirteen time slots:
one Tag Slot followed by twelve Data Slots. The Tag Slot, Slot 0, contains 16 bits of which 5 are used by the
LM4549B. One is used to indicate that the AC Link interface is fully operational and the other 4 to indicate the
validity of the data in the four of the twelve following Data Slots that are used by the LM4549B. Each Frame
consists of 256 bits with each of the twelve data slots containing 20 bits.
A new Input Frame is signaled with a low-to-high transition of SYNC. SYNC should be clocked from the controller
on a rising edge of BIT_CLK and, as shown in Figure 20 and Figure 21, the first tag bit in the Frame (“Codec
Ready”) is clocked from the LM4549B by the next rising edge of BIT_CLK. The LM4549B always clocks data to
SDATA_IN on a rising edge of BIT_CLK and the controller is expected to sample SDATA_IN on the next falling
edge. The LM4549B samples SYNC on the falling edge of BIT_CLK.
Input and Output Frames are aligned to the same SYNC transition.
The LM4549B checks each Frame to ensure 256 bits are received. If a new Frame is detected (a low-to-high
transition on SYNC) before 256 bits are received from an old Frame then the new Frame is ignored i.e. no valid
data is sent on SDATA_IN until a valid new Frame is detected.
The LM4549B transmits data MSB first, in a MSB justified format. All reserved bits and slots are stuffed with "0"s
by the LM4549B.
Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: LM4549B