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LM4549B

www.ti.com

SNAS598A –JULY 2012–REVISED MAY 2013

LM4549B AC '97 Rev 2.1 Multi-Channel Audio Codec with Sample Rate Conversion and TI

3D Sound

Check for Samples: LM4549B

FEATURES

DESCRIPTION

The LM4549B is an audio codec for PC systems

• AC '97 Rev 2.1 Compliant

which is fully PC99 compliant and performs the

• High Quality Sample Rate Conversion from 4

analog intensive functions of the AC '97 Rev 2.1

kHz to 48 kHz in 1 Hz Increments

architecture. Using 18-bit Sigma-Delta ADCs and

• Multiple Codec Support

DACs, the LM4549B provides 90 dB of Dynamic

Range.

• True Line Level Output with Separate Gain

Control

The LM4549B was designed specifically to provide a

high quality audio path and provide all analog

• Texas Instrument's 3D Sound Stereo

functionality in a PC audio system. It features full

Enhancement Circuitry

duplex stereo ADCs and DACs and analog mixers

• Advanced Power Management Support

with access to 4 stereo and 4 mono inputs. Each

• External Amplifier Power Down (EAPD)

mixer input has separate gain, attenuation and mute

Control

control and the mixers drive 1 mono and 2 stereo

outputs, each with attenuation and mute control. The

• PC-Beep Passthrough to Line Out During

LM4549B supports Texas Instrument's 3D Sound

Initialization or Cold Reset

stereo enhancement and a comprehensive sample

• Digital 3.3V and 5V Supply Options

rate conversion capability. The sample rate for the

• Extended Temperature: −40°C ≤ T

≤ 85°C

ADCs and DACs can be programmed separately with

a resolution of 1 Hz to convert any rate in the range 4

kHz – 48 kHz. Sample timing from the ADCs and

APPLICATIONS

sample request timing for the DACs are completely

• Desktop PC Audio Systems on PCI Cards,

deterministic to ease task scheduling and application

AMR Cards, or with Motherboard Chips Sets

software development. These features together with

Featuring AC Link

an extended temperature range also make the

LM4549B suitable for non-PC codec applications.

• Portable PC Systems as on MDC Cards, or

with a Chipset or Accelerator Featuring AC

The LM4549B features the ability to connect several

Link

codecs together using the Extended AC Link

configuration of one dedicated serial data signal to

• General and Multi-Channel Audio Frequency

the Controller per codec. LM4549B systems support

Systems

up to 8 simultaneous channels of streaming data on

• Automotive Telematics

Input Frames (Codec to Controller) while Output

Frames (Controller to Codec) carry 2 streams to

KEY SPECIFICATIONS

multiple codecs. The LM4549B may also be used in

systems with the Texas Instruments LM4550B to

• Analog Mixer Dynamic Range: 97 dB (typ)

support up to 6 simultaneous channels of streaming

• DAC Dynamic Range: 89 dB (typ)

data on Output Frames.

• ADC Dynamic Range: 90 dB (typ)

The AC '97 architecture separates the analog and

digital functions of the PC audio system allowing both

for system design flexibility and increased

performance.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (39 pages)

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LM4549B www.ti.com SNAS598A – JULY 2012 – REVISED MAY 2013 LM4549B AC '97 Rev 2.1 Multi-Channel Audio Codec with Sample Rate Conversion and TI 3D Sound Check for Samples: LM4549B FEATURES DESCRIPTION • • The LM4549B is an audio codec for PC systems which is fully PC99 compliant and performs the analog intensive functions of the AC '97 Rev 2.1 architecture. Using 18-bit Sigma-Delta ADCs and DACs, the LM4549B provides 90 dB of Dynamic Range. 1 2 • • • • • • • • AC '97 Rev 2.
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LM4549B SNAS598A – JULY 2012 – REVISED MAY 2013 www.ti.
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LM4549B www.ti.com SNAS598A – JULY 2012 – REVISED MAY 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) Supply Voltage 6.0V −65°C to +150°C Storage Temperature −0.3V to VDD +0.
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LM4549B SNAS598A – JULY 2012 – REVISED MAY 2013 www.ti.com Electrical Characteristics (1)(2) (continued) The following specifications apply for AVDD = 5V, DVDD = 3.3V, Fs = 48 kHz, single codec configuration, (primary mode) unless otherwise noted. Limits apply for TA= 25°C. The reference for 0 dB is 1 Vrms unless otherwise specified.
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LM4549B www.ti.com SNAS598A – JULY 2012 – REVISED MAY 2013 Electrical Characteristics (1)(2) (continued) The following specifications apply for AVDD = 5V, DVDD = 3.3V, Fs = 48 kHz, single codec configuration, (primary mode) unless otherwise noted. Limits apply for TA= 25°C. The reference for 0 dB is 1 Vrms unless otherwise specified. LM4549B Symbol Parameter Conditions Typical (3) Limit Units (Limits) (4) VIH High level input voltage 0.65 x DVDD V (min) VIL Low level input voltage 0.
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LM4549B SNAS598A – JULY 2012 – REVISED MAY 2013 www.ti.com Timing Diagrams TBCH BIT_CLK TBCL TBCP TSH SYNC TSL TSP Figure 1. Clocks BIT_CLK TCO SDATA_IN TDHOLD TDSETUP SDATA_OUT TS SYNC THOLD Figure 2. Data Delay, Setup and Hold SYNC BIT_CLK SDATA_IN SDATA_OUT TRISE TFALL 90% 90% 10% 10% Figure 3. Digital Rise and Fall Input: VIH Output: VOH Input: VIL Output: VOL Figure 4.
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LM4549B www.ti.com SNAS598A – JULY 2012 – REVISED MAY 2013 TRST_LOW TRST2CLK RESET# BIT_CLK TSUPPLY2RST DVDD (min), AVDD (min) DVDD, AVDD Figure 5. Power On Reset TRST_LOW TRST2CLK RESET# BIT_CLK Figure 6. Cold Reset TSH TSYNC2CLK SYNC BIT_CLK Figure 7.
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LM4549B SNAS598A – JULY 2012 – REVISED MAY 2013 www.ti.com Typical Application AVDD 3.3V or 5V Digital Supply 5V Analog Supply + + 0.1 PF 1 PF 1.0 PF Mono Inputs 1.0 PF 21 + 1.0 PF 14 15 22 + 1.0 PF 1.0 PF Microphone Inputs 12 13 DVDD1 LINE_OUT_L LINE_IN_R LINE_OUT_R CD_L LNLVL_OUT_L CD_GND LNLVL_OUT_R CD_R VIDEO_L MONO_OUT VIDEO_R Z97 Digital Controller 6 8 10 11 33 pF 2 1 M: 33 pF 3 36 39 41 37 1.0 PF 1.0 PF 1.0 PF 1.0 PF 1.
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LM4549B www.ti.com SNAS598A – JULY 2012 – REVISED MAY 2013 Digital +3.3V Supply +7.5V - +20V C33 0.33 PF PC_BEEP AUXILIARY INPUT HEADER 2 C24 R17 1 PF 6.81k R16 C11 0.1 PF C23 + 6.81k Optional for LM4549B. Will improve transient response 4 7 C22 12 1 PF 15 14 20 19 18 24 23 28 C21 + 6.81k R11 1 PF 6.81k C20 + R10 6.81k R8 21 C19 6.81k 22 C12 17 0.1 PF 16 13 R7 1 PF 6.81k R6 C18 C13 0.1 PF R4 C7 2.2k 220 pF R3 C17 C30 2.2 PF C31 3.
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LM4549B SNAS598A – JULY 2012 – REVISED MAY 2013 www.ti.com Connection Diagram MONO_OUT NC LNLVL_OUT_L NC LNLVL_OUT_R NC NC NC ID0# ID1# EAPD NC Top View 48 47 46 45 44 43 42 41 40 39 38 37 DVDD1 1 36 LINE_OUT_R XTL_IN 2 35 LINE_OUT_L XTL_OUT DVSS1 3 34 3DP 4 33 3DN SDATA_OUT 5 32 NC BIT_CLK DVSS2 6 31 NC 30 NC SDATA_IN DVDD2 8 29 LM4549B $& µ97 Rev 2.
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LM4549B www.ti.com SNAS598A – JULY 2012 – REVISED MAY 2013 ANALOG I/O (continued) Name VIDEO_L VIDEO_R CD_L CD_GND CD_R MIC1 MIC2 LINE_IN_L Pin 16 17 18 19 20 21 22 23 I/O Functional Description I Left Stereo Channel Input This line level input (1 Vrms nominal) is selectable at the left channel of the stereo Record Select Mux for conversion by the left channel ADC.
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LM4549B SNAS598A – JULY 2012 – REVISED MAY 2013 www.ti.com ANALOG I/O (continued) Name LINE_IN_R LINE_OUT_L LINE_OUT_R MONO_OUT LNLVL_OUT_L LNLVL_OUT_R Pin I/O I O Left Stereo Channel Output This line level output (1 Vrms nominal) is fed from the left channel of the Stereo Mix signal from MIX2 via the Master Volume register, 02h. The LINE_OUT_L amplitude can be muted (along with LINE_OUT_R) or adjusted from 0 dB to -46.5 dB in 1.5 dB steps.
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LM4549B www.ti.com SNAS598A – JULY 2012 – REVISED MAY 2013 DIGITAL I/O AND CLOCKING (continued) Name SYNC RESET# ID0# ID1# Pin 10 11 45 46 I/O Functional Description I AC Link frame marker and Warm Reset This input defines the boundaries of AC Link frames. Each frame lasts 256 periods of BIT_CLK. In normal operation SYNC is a 48 kHz positive pulse with a duty cycle of 6.25% (16/256).
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LM4549B SNAS598A – JULY 2012 – REVISED MAY 2013 www.ti.com Typical Performance Characteristics 14 ADC Noise Floor DAC Noise Floor Figure 11. Figure 12. Line Out Noise Floor (Analog Loopthrough) Line Level Out Noise Floor (Analog Loopthrough) Figure 13. Figure 14. ADC Frequency Response DAC Frequency Response Figure 15. Figure 16.
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LM4549B www.ti.
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LM4549B SNAS598A – JULY 2012 – REVISED MAY 2013 16 www.ti.
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LM4549B www.ti.com SNAS598A – JULY 2012 – REVISED MAY 2013 FUNCTIONAL DESCRIPTION GeneraL The LM4549B codec can mix, process and convert among analog (stereo and mono) and digital (AC Link format) inputs and outputs. There are four stereo and four mono analog inputs and two stereo and one mono analog outputs. A single codec supports data streaming on two input and two output channels of the AC Link digital interface simultaneously.
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LM4549B SNAS598A – JULY 2012 – REVISED MAY 2013 www.ti.com Stereo Outputs The output volume from LINE_OUT and LNLVL_OUT can be muted or adjusted by 0 dB to 45 dB in nominal 3 dB steps under the control of the output volume registers Master Volume (02h) and Line Level Volume (04h) respectively. As with the input volume registers, adjustments to the levels of the two stereo channels can be made independently but both left and right channels share a mute bit (D15).
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LM4549B www.ti.com SNAS598A – JULY 2012 – REVISED MAY 2013 Tag Phase Data Phase 20.8 Ps (48 kHz) SYNC BIT_CLK SDATA_OUT End of previous Audio Frame Valid Frame Slot (1) Slot (4) ID1 ID0 Tag bits: &Œ u v ^o}š ^s o] _ ]š•, Codec ID Slot (x) = ³1´ LQGLFDWHV WLPH VORW x contains valid PCM data Codec ID = (ID1, ID0) - codec address for multiple codecs Bit 19 Bit 0 SLOT 1 Read / Write Request, Command Address Bit 19 Slot 2 Bit 0 Slot 12 SLOTS 2 to 12 Data: Command and Audio Figure 18.
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LM4549B SNAS598A – JULY 2012 – REVISED MAY 2013 www.ti.com LM4549B samples SYNC assertion LM4549B samples first bit of SDATA_OUT SYNC BIT_CLK Valid Frame SDATA_OUT Slot (1) Slot (2) End of previous Audio Frame Figure 19. Start of AC Link Output Frame Table 1. Slot 0, Output Frame Bit Description Comment 15 Valid Frame 1= Valid data in at least one slot.
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LM4549B www.ti.com SNAS598A – JULY 2012 – REVISED MAY 2013 SDATA_OUT: Slots 3 & 4 – PCM Playback Left/Right Channels Slots 3 and 4 are 20-bit fields used to transmit PCM data to the left and right channels of the stereo DAC for all codec Primary and Secondary modes. Any unused bits should be stuffed with zeros. The LM4549B DACs have 18-bit resolution and will therefore use the 18 MSBs of the 20-bit PCM data (MSB justified). Table 4.
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LM4549B SNAS598A – JULY 2012 – REVISED MAY 2013 www.ti.com LM4549B samples SYNC assertion LM4549B outputs first bit of SDATA_IN SYNC BIT_CLK SDATA_IN Codec Ready Slot (1) Slot (2) End of previous Audio Frame Figure 21. Start of AC Link Input Frame SDATA_IN: Slot 0 – Codec/Slot Status Bits The first bit (bit 15, “Codec Ready”) of slot 0 in the AC Link Input Frame indicates when the codec's AC Link digital interface and its status/control registers are fully operational.
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LM4549B www.ti.com SNAS598A – JULY 2012 – REVISED MAY 2013 resolution of 1 Hz) is supported. Slot Requests from the LM4549B are issued completely deterministically. For example if a sample rate of 8000 Hz is programmed into 2Ch then the LM4549B will always issue a slot request in every sixth frame. A frequency of 9600 Hz will result in a request every fifth frame while a frequency of 8800 Hz will cause slot requests to be spaced alternately five and six frames apart.
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LM4549B SNAS598A – JULY 2012 – REVISED MAY 2013 www.ti.com This is a 20-bit slot and the digitized 18-bit PCM data is transmitted in an MSB justified format. The remaining 2 LSBs are stuffed with zeros. Table 9.
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LM4549B www.ti.com SNAS598A – JULY 2012 – REVISED MAY 2013 Mute MM5:MM0 0 0 00000 0 dB attenuation Function 0 0 11111 46.5 dB attenuation 0 1 xxxxx As written 0 0 11111 As read back 1 X XXXXX *mute Default: 8000h PC Beep Volume Register (0Ah) This input register adjusts the level of the mono PC_BEEP input to the stereo mixer MIX2 where it is summed equally into both channels of the Stereo Mix signal.
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LM4549B SNAS598A – JULY 2012 – REVISED MAY 2013 www.ti.com SR2:SR0 Source for Right Channel ADC 0 *Mic input 1 CD input (R) 2 VIDEO input (R) 3 AUX input (R) 4 LINE_IN input (R) 5 Stereo Mix (R) 6 Mono Mix 7 PHONE input Default: 0000h Record Gain Register (1Ch) This register controls the input levels for both channels of the stereo ADC. The inputs come from the Record Select Mux and are selected via the Record Select Control register, 1Ah.
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LM4549B www.ti.com SNAS598A – JULY 2012 – REVISED MAY 2013 3D Control Register (22h) This read-only (0101h) register indicates, in accordance with the AC '97 Rev 2.1 Specification, the fixed depth and center characteristics of the TI 3D Sound stereo enhancement. Powerdown Control / Status Register (26h) This read/write register is used both to monitor subsystem readiness and also to program the LM4549B powerdown states. The 4 LSBs indicate status and 7 of the 8 MSBs control powerdown.
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LM4549B SNAS598A – JULY 2012 – REVISED MAY 2013 www.ti.com Pin 46 (ID1#) Pin 45 (ID0#) D15,28h (ID1) D14,28h (ID0) Codec Identity Mode NC/DVDD NC/DVDD 0 0 Primary NC/DVDD GND 0 1 Secondary 1 GND NC/DVDD 1 0 Secondary 2 GND GND 1 1 Secondary 3 Extended Audio Status/Control register (2Ah) This read/write register provides status and control of the variable sample rate capabilities in the LM4549B.
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LM4549B www.ti.com SNAS598A – JULY 2012 – REVISED MAY 2013 PR0 controls the powerdown state of the ADC and associated sampling rate conversion circuitry. PR1 controls powerdown for the DAC and the DAC sampling rate conversion circuitry. PR2 powers down the mixer circuits (MIX1, MIX2, TI 3D Sound, Mono Out, Line Out). PR3 powers down VREF in addition to all the same mixer circuits as PR2. PR4 powers down the AC Link Digital Interface – see Figure 22 for signal powerdown timing.
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LM4549B SNAS598A – JULY 2012 – REVISED MAY 2013 www.ti.com The bandgap reference and the anti-pop slow turn-on circuit were improved in the LM4549B. A pullup resistor is not required on VREF, pin 27. For an existing design, the 10 kΩ resistor can be left on the pc board, but the temperature coefficient will improve with no resistor on this pin. In addition, the THD will improve by 0.2–0.5 dB. The external capacitor is charged by an internal current source, ramping the voltage slowly.
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LM4549B www.ti.com SNAS598A – JULY 2012 – REVISED MAY 2013 When reading from a Secondary Codec, the controller must send the correct Codec ID bits (i.e. the target Codec Identity in slot 0, bits 1 and 0) along with the read-request bit (slot 1, bit 19) and target register address (slot 1, bits 18 – 12).
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LM4549B SNAS598A – JULY 2012 – REVISED MAY 2013 www.ti.
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LM4549B www.ti.com SNAS598A – JULY 2012 – REVISED MAY 2013 REVISION HISTORY Changes from Original (May 2013) to Revision A • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 24-Nov-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device LM4549BVHX/NOPB Package Package Pins Type Drawing LQFP PT 48 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 16.4 Pack Materials-Page 1 9.3 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 9.3 2.2 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM4549BVHX/NOPB LQFP PT 48 1000 367.0 367.0 38.
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MECHANICAL DATA MTQF003A – OCTOBER 1994 – REVISED DECEMBER 1996 PT (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 1,45 1,35 Seating Plane 1,60 MAX 0°– 7° 0,75 0,45 0,10 4040052 / C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.