Datasheet

1
2
3
4
5
10
9
8
7
6
Die-Attach Pad: GND
1
2
3
4
5
10
9
8
7
6
Die-Attach Pad: GND
SW
PGND
VIN
EN
SS
Top View
Bottom View
VOUT
N/C
FB
COMP
AGND
I
OUT
(mA)
EFFICIENCY (%)
100
90
80
70
60
50
40
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70
V
IN
= 5.5V
V
IN
= 4.5V
V
IN
= 2.7V
V
IN
= 3.6V
LM4510
SNVS533C –SEPTEMBER 2007–REVISED MAY 2013 www.ti.com
DESCRIPTION (CONTINUED)
The LM4510 features advanced short-circuit protection to maximize safety during output to ground short
condition. During shutdown the feedback resistors and the load are disconnected from the input to prevent
leakage current paths to ground.
The LM4510 is available in a 10-pin thermally enhanced Leadless Leadframe Package: SON-10.
Figure 2. Efficiency at V
OUT
= 16V
Connection Diagram
Figure 3. SON-10 No Pullback Package, 3mm x 3mm x 0.8mm
See Package Number DSC0010A
Pin Descriptions
Name Pin Description
SW 1 Switch pin. Drain connections of both internal NMOS and PMOS devices.
PGND 2 Power ground
VIN 3 Analog and Power supply input. Input range: 2.7V to 5.5V.
EN 4 Enable logic input. HIGH= Enabled, LOW=Shutdown.
SS 5 Soft-start pin
AGND 6 Analog ground
COMP 7 Compensation network connection.
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