Datasheet

3 Cortex-M3 Peripherals
This chapter provides information on the Stellaris
®
implementation of the Cortex-M3 processor
peripherals, including:
■ SysTick (see page 98)
Provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible
control mechanism.
■ Nested Vectored Interrupt Controller (NVIC) (see page 99)
– Facilitates low-latency exception and interrupt handling
– Controls power management
– Implements system control registers
■ System Control Block (SCB) (see page 101)
Provides system implementation information and system control, including configuration, control,
and reporting of system exceptions.
■ Memory Protection Unit (MPU) (see page 101)
Supports the standard ARMv7 Protected Memory System Architecture (PMSA) model. The MPU
provides full support for protection regions, overlapping protection regions, access permissions,
and exporting memory attributes to the system.
Table 3-1 on page 98 shows the address map of the Private Peripheral Bus (PPB). Some peripheral
register regions are split into two address regions, as indicated by two addresses listed.
Table 3-1. Core Peripheral Register Regions
Description (see page ...)Core PeripheralAddress
98System Timer0xE000.E010-0xE000.E01F
99Nested Vectored Interrupt Controller0xE000.E100-0xE000.E4EF
0xE000.EF00-0xE000.EF03
101System Control Block0xE000.ED00-0xE000.ED3F
101Memory Protection Unit0xE000.ED90-0xE000.EDB8
3.1 Functional Description
This chapter provides information on the Stellaris implementation of the Cortex-M3 processor
peripherals: SysTick, NVIC, SCB and MPU.
3.1.1 System Timer (SysTick)
Cortex-M3 includes an integrated system timer, SysTick, which provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example as:
■ An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick
routine.
■ A high-speed alarm timer using the system clock.
June 18, 201298
Texas Instruments-Production Data
Cortex-M3 Peripherals
NRND: Not recommended for new designs.