Datasheet

In addition, if the SEVONPEND bit in the SYSCTRL register is set, any new pending interrupt triggers
an event and wakes up the processor, even if the interrupt is disabled or has insufficient priority to
cause exception entry. For more information about SYSCTRL, see page 133.
2.8 Instruction Set Summary
The processor implements a version of the Thumb instruction set. Table 2-13 on page 95 lists the
supported instructions.
Note: In Table 2-13 on page 95:
■ Angle brackets, <>, enclose alternative forms of the operand
■ Braces, {}, enclose optional operands
■ The Operands column is not exhaustive
■ Op2 is a flexible second operand that can be either a register or a constant
■ Most instructions can use an optional condition code suffix
For more information on the instructions and operands, see the instruction descriptions in
the Cortex™-M3/M4 Instruction Set Technical User's Manual.
Table 2-13. Cortex-M3 Instruction Summary
FlagsBrief DescriptionOperandsMnemonic
N,Z,C,VAdd with carry{Rd,} Rn, Op2ADC, ADCS
N,Z,C,VAdd{Rd,} Rn, Op2ADD, ADDS
N,Z,C,VAdd{Rd,} Rn , #imm12ADD, ADDW
-Load PC-relative addressRd, labelADR
N,Z,CLogical AND{Rd,} Rn, Op2AND, ANDS
N,Z,CArithmetic shift rightRd, Rm, <Rs|#n>ASR, ASRS
-BranchlabelB
-Bit field clearRd, #lsb, #widthBFC
-Bit field insertRd, Rn, #lsb, #widthBFI
N,Z,CBit clear{Rd,} Rn, Op2BIC, BICS
-Breakpoint#immBKPT
-Branch with linklabelBL
-Branch indirect with linkRmBLX
-Branch indirectRmBX
-Compare and branch if non-zeroRn, labelCBNZ
-Compare and branch if zeroRn, labelCBZ
-Clear exclusive-CLREX
-Count leading zerosRd, RmCLZ
N,Z,C,VCompare negativeRn, Op2CMN
N,Z,C,VCompareRn, Op2CMP
-Change processor state, disable
interrupts
iCPSID
-Change processor state, enable
interrupts
iCPSIE
-Data memory barrier-DMB
-Data synchronization barrier-DSB
95June 18, 2012
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Stellaris
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LM3S8962 Microcontroller
NRND: Not recommended for new designs.