Datasheet

16 Ethernet Controller .............................................................................................. 598
16.1 Block Diagram ............................................................................................................ 598
16.2 Signal Description ....................................................................................................... 599
16.3 Functional Description ................................................................................................. 601
16.3.1 MAC Operation ........................................................................................................... 601
16.3.2 Internal MII Operation .................................................................................................. 604
16.3.3 PHY Operation ............................................................................................................ 604
16.3.4 Interrupts .................................................................................................................... 606
16.4 Initialization and Configuration ..................................................................................... 606
16.4.1 Hardware Configuration ............................................................................................... 606
16.4.2 Software Configuration ................................................................................................ 607
16.5 Ethernet Register Map ................................................................................................. 608
16.6 Ethernet MAC Register Descriptions ............................................................................. 609
16.7 MII Management Register Descriptions ......................................................................... 628
17 Analog Comparator .............................................................................................. 647
17.1 Block Diagram ............................................................................................................ 647
17.2 Signal Description ....................................................................................................... 647
17.3 Functional Description ................................................................................................. 648
17.3.1 Internal Reference Programming .................................................................................. 649
17.4 Initialization and Configuration ..................................................................................... 650
17.5 Register Map .............................................................................................................. 650
17.6 Register Descriptions .................................................................................................. 651
18 Pulse Width Modulator (PWM) ............................................................................ 659
18.1 Block Diagram ............................................................................................................ 660
18.2 Signal Description ....................................................................................................... 661
18.3 Functional Description ................................................................................................. 662
18.3.1 PWM Timer ................................................................................................................. 662
18.3.2 PWM Comparators ...................................................................................................... 662
18.3.3 PWM Signal Generator ................................................................................................ 663
18.3.4 Dead-Band Generator ................................................................................................. 664
18.3.5 Interrupt/ADC-Trigger Selector ..................................................................................... 664
18.3.6 Synchronization Methods ............................................................................................ 665
18.3.7 Fault Conditions .......................................................................................................... 665
18.3.8 Output Control Block ................................................................................................... 665
18.4 Initialization and Configuration ..................................................................................... 665
18.5 Register Map .............................................................................................................. 666
18.6 Register Descriptions .................................................................................................. 668
19 Quadrature Encoder Interface (QEI) ................................................................... 698
19.1 Block Diagram ............................................................................................................ 698
19.2 Signal Description ....................................................................................................... 699
19.3 Functional Description ................................................................................................. 700
19.4 Initialization and Configuration ..................................................................................... 702
19.5 Register Map .............................................................................................................. 702
19.6 Register Descriptions .................................................................................................. 703
20 Pin Diagram .......................................................................................................... 716
21 Signal Tables ........................................................................................................ 718
21.1 100-Pin LQFP Package Pin Tables ............................................................................... 718
June 18, 20128
Texas Instruments-Production Data
Table of Contents
NRND: Not recommended for new designs.