Datasheet

Figure 23-9. Watchdog Reset Timing
WDOG
Reset
(Internal)
/Reset
(Internal)
R9
23.2.5 Sleep Modes
Table 23-16. Sleep Modes AC Characteristics
a
UnitMaxNomMinParameter NameParameterParameter No
system clocks7--Time to wake from interrupt in sleep or
deep-sleep mode, not using the PLL
t
WAKE_S
D1
msT
READY
--Time to wake from interrupt in sleep or
deep-sleep mode when using the PLL
t
WAKE_PLL_S
D2
a. Values in this table assume the IOSC is the clock source during sleep or deep-sleep mode.
23.2.6 Hibernation Module
The Hibernation Module requires special system implementation considerations since it is intended
to power-down all other sections of its host device. The system power-supply distribution and
interfaces to the device must be driven to 0 V
DC
or powered down with the same external voltage
regulator controlled by HIB.
The external voltage regulators controlled by HIB must have a settling time of 250 μs or less.
Table 23-17. Hibernation Module AC Characteristics
UnitMaxNomMinParameter NameParameterParameter
No
μs-200-Internal 32.768 KHz clock reference rising
edge to /HIB asserted
t
HIB_LOW
H1
μs-30-Internal 32.768 KHz clock reference rising
edge to /HIB deasserted
t
HIB_HIGH
H2
μs--62/WAKE assertion timet
WAKE_ASSERT
H3
μs124-62/WAKE assert to /HIB desassertt
WAKETOHIB
H4
ms--20XOSC settling time
a
t
XOSC_SETTLE
H5
μs--92Access time to or from a non-volatile register
in HIB module to complete
t
HIB_REG_ACCESS
H6
μs250--HIB deassert to VDD and VDD25 at minimum
operational level
t
HIB_TO_VDD
H7
a. This parameter is highly sensitive to PCB layout and trace lengths, which may make this parameter time longer. Care
must be taken in PCB design to minimize trace lengths and RLC (resistance, inductance, capacitance).
757June 18, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S8962 Microcontroller
NRND: Not recommended for new designs.