Datasheet

Figure 23-3. JTAG Test Access Port (TAP) Timing
TDO Output Valid
TCK
TDO Output Valid
J12
TDO
TDI
TMS
TDI Input Valid TDI Input Valid
J13
J9 J10
TMS Input Valid
J9 J10
TMS Input Valid
J11
J7 J8J8J7
Figure 23-4. JTAG TRST Timing
TCK
J14 J15
TRST
23.2.4 Reset
Table 23-15. Reset Characteristics
UnitMaxNomMinParameter NameParameterParameter
No.
V-2.0-Reset thresholdV
TH
R1
V2.952.92.85Brown-Out thresholdV
BTH
R2
ms-10-Power-On Reset timeoutT
POR
R3
µs-500-Brown-Out timeoutT
BOR
R4
ms11-6Internal reset timeout after PORT
IRPOR
R5
µs1-0Internal reset timeout after BOR
a
T
IRBOR
R6
ms1-0Internal reset timeout after hardware reset
(RST pin)
T
IRHWR
R7
µs20-2.5Internal reset timeout after software-initiated
system reset
a
T
IRSWR
R8
µs20-2.5Internal reset timeout after watchdog reset
a
T
IRWDR
R9
ms100--Supply voltage (V
DD
) rise time (0V-3.3V),
power on reset
T
VDDRISE
R10
µs250--Supply voltage (V
DD
) rise time (0V-3.3V),
waking from hibernation
755June 18, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S8962 Microcontroller
NRND: Not recommended for new designs.