Datasheet

Table 21-6. Signals by Signal Name (continued)
DescriptionBuffer Type
a
Pin TypePin NumberPin Name
GPIO port D bit 1.TTLI/OG2PD1
GPIO port D bit 2.TTLI/OH2PD2
GPIO port D bit 3.TTLI/OH1PD3
GPIO port D bit 4.TTLI/OE1PD4
GPIO port D bit 5.TTLI/OE2PD5
GPIO port D bit 6.TTLI/OF2PD6
GPIO port D bit 7.TTLI/OF1PD7
GPIO port E bit 0.TTLI/OA11PE0
GPIO port E bit 1.TTLI/OB12PE1
GPIO port E bit 2.TTLI/OB11PE2
GPIO port E bit 3.TTLI/OA12PE3
GPIO port F bit 0.TTLI/OM9PF0
GPIO port F bit 1.TTLI/OH12PF1
GPIO port F bit 2.TTLI/OJ11PF2
GPIO port F bit 3.TTLI/OJ12PF3
GPIO port G bit 0.TTLI/OK1PG0
GPIO port G bit 1.TTLI/OK2PG1
QEI module 0 phase A.TTLIL1PhA0
QEI module 1 phase A.TTLIA12PhA1
QEI module 0 phase B.TTLIM2PhB0
QEI module 1 phase B.TTLIB11PhB1
PWM 0. This signal is controlled by PWM Generator 0.TTLOM9PWM0
PWM 1. This signal is controlled by PWM Generator 0.TTLOK2PWM1
PWM 2. This signal is controlled by PWM Generator 1.TTLOE12PWM2
PWM 3. This signal is controlled by PWM Generator 1.TTLOD12PWM3
PWM 4. This signal is controlled by PWM Generator 2.TTLOA11PWM4
PWM 5. This signal is controlled by PWM Generator 2.TTLOB12PWM5
System reset input.TTLIH11RST
RXIN of the Ethernet PHY.AnalogIL7RXIN
RXIP of the Ethernet PHY.AnalogIM7RXIP
SSI module 0 clockTTLI/OM4SSI0Clk
SSI module 0 frame signalTTLI/OL4SSI0Fss
SSI module 0 receiveTTLIL5SSI0Rx
SSI module 0 transmitTTLOM5SSI0Tx
JTAG/SWD CLK.TTLIA9SWCLK
JTAG TMS and SWDIO.TTLI/OB9SWDIO
JTAG TDO and SWO.TTLOA10SWO
JTAG/SWD CLK.TTLIA9TCK
JTAG TDI.TTLIB8TDI
JTAG TDO and SWO.TTLOA10TDO
JTAG TMS and SWDIO.TTLI/OB9TMS
June 18, 2012738
Texas Instruments-Production Data
Signal Tables
NRND: Not recommended for new designs.