Datasheet

Table 21-5. Signals by Pin Number (continued)
DescriptionBuffer Type
a
Pin TypePin NamePin Number
The positive supply for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to minimize
the electrical noise contained on VDD from affecting the analog
functions. VDDA pins must be supplied with a voltage that meets
the specification in “Recommended DC Operating
Conditions” on page 748, regardless of system implementation.
Power-VDDA
C7
GND of the Ethernet PHY.Power-GNDPHY
C8
GND of the Ethernet PHY.Power-GNDPHY
C9
VCC of the Ethernet PHY.Power-VCCPHY
C10
GPIO port B bit 2.TTLI/OPB2
C11
I
2
C module 0 clock.ODI/OI2C0SCL
GPIO port B bit 3.TTLI/OPB3
C12
I
2
C module 0 data.ODI/OI2C0SDA
No connect. Leave the pin electrically unconnected/isolated.--NCD1
No connect. Leave the pin electrically unconnected/isolated.--NCD2
Positive supply for most of the logic function, including the
processor core and most peripherals.
Power-VDD25
D3
VCC of the Ethernet PHY.Power-VCCPHY
D10
VCC of the Ethernet PHY.Power-VCCPHY
D11
GPIO port B bit 1.TTLI/OPB1
D12
PWM 3. This signal is controlled by PWM Generator 1.TTLOPWM3
GPIO port D bit 4.TTLI/OPD4
E1
Capture/Compare/PWM 0.TTLI/OCCP0
GPIO port D bit 5.TTLI/OPD5
E2
Low drop-out regulator output voltage. This pin requires an external
capacitor between the pin and GND of 1 µF or greater. The LDO
pin must also be connected to the VDD25 pins at the board level
in addition to the decoupling capacitor(s).
Power-LDO
E3
Positive supply for I/O and some logic.Power-VDD33
E10
CPU Mode bit 0. Input must be set to logic 0 (grounded); other
encodings reserved.
TTLICMOD0
E11
GPIO port B bit 0.TTLI/OPB0
E12
PWM 2. This signal is controlled by PWM Generator 1.TTLOPWM2
GPIO port D bit 7.TTLI/OPD7
F1
QEI module 0 index.TTLIIDX0
GPIO port D bit 6.TTLI/OPD6
F2
PWM Fault.TTLIFault
Positive supply for most of the logic function, including the
processor core and most peripherals.
Power-VDD25
F3
Ground reference for logic and I/O pins.Power-GND
F10
Ground reference for logic and I/O pins.Power-GND
F11
Ground reference for logic and I/O pins.Power-GND
F12
GPIO port D bit 0.TTLI/OPD0
G1
CAN module 0 receive.TTLICAN0Rx
733June 18, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S8962 Microcontroller
NRND: Not recommended for new designs.