Datasheet

Table 21-5. Signals by Pin Number (continued)
DescriptionBuffer Type
a
Pin TypePin NamePin Number
GPIO port C bit 0.TTLI/OPC0
A9
JTAG/SWD CLK.TTLISWCLK
JTAG/SWD CLK.TTLITCK
GPIO port C bit 3.TTLI/OPC3
A10
JTAG TDO and SWO.TTLOSWO
JTAG TDO and SWO.TTLOTDO
GPIO port E bit 0.TTLI/OPE0
A11
PWM 4. This signal is controlled by PWM Generator 2.TTLOPWM4
GPIO port E bit 3.TTLI/OPE3
A12
QEI module 1 phase A.TTLIPhA1
Analog-to-digital converter input 0.AnalogIADC0
B1
Analog-to-digital converter input 3.AnalogIADC3
B2
Analog-to-digital converter input 2.AnalogIADC2
B3
No connect. Leave the pin electrically unconnected/isolated.--NCB4
The ground reference for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from GND to minimize
the electrical noise contained on VDD from affecting the analog
functions.
Power-GNDA
B5
Ground reference for logic and I/O pins.Power-GND
B6
GPIO port B bit 5.TTLI/OPB5
B7
Analog comparator 0 output.TTLOC0o
GPIO port C bit 2.TTLI/OPC2
B8
JTAG TDI.TTLITDI
GPIO port C bit 1.TTLI/OPC1
B9
JTAG TMS and SWDIO.TTLI/OSWDIO
JTAG TMS and SWDIO.TTLI/OTMS
CPU Mode bit 1. Input must be set to logic 0 (grounded); other
encodings reserved.
TTLICMOD1
B10
GPIO port E bit 2.TTLI/OPE2
B11
QEI module 1 phase B.TTLIPhB1
GPIO port E bit 1.TTLI/OPE1
B12
PWM 5. This signal is controlled by PWM Generator 2.TTLOPWM5
No connect. Leave the pin electrically unconnected/isolated.--NCC1
No connect. Leave the pin electrically unconnected/isolated.--NCC2
Positive supply for most of the logic function, including the
processor core and most peripherals.
Power-VDD25
C3
Ground reference for logic and I/O pins.Power-GND
C4
Ground reference for logic and I/O pins.Power-GND
C5
The positive supply for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to minimize
the electrical noise contained on VDD from affecting the analog
functions. VDDA pins must be supplied with a voltage that meets
the specification in “Recommended DC Operating
Conditions” on page 748, regardless of system implementation.
Power-VDDA
C6
June 18, 2012732
Texas Instruments-Production Data
Signal Tables
NRND: Not recommended for new designs.