Datasheet

Table 21-1. Signals by Pin Number (continued)
DescriptionBuffer Type
a
Pin TypePin NamePin Number
GPIO port B bit 1.TTLI/OPB1
67
PWM 3. This signal is controlled by PWM Generator 1.TTLOPWM3
Positive supply for I/O and some logic.Power-VDD
68
Ground reference for logic and I/O pins.Power-GND
69
GPIO port B bit 2.TTLI/OPB2
70
I
2
C module 0 clock.ODI/OI2C0SCL
GPIO port B bit 3.TTLI/OPB3
71
I
2
C module 0 data.ODI/OI2C0SDA
GPIO port E bit 0.TTLI/OPE0
72
PWM 4. This signal is controlled by PWM Generator 2.TTLOPWM4
GPIO port E bit 1.TTLI/OPE1
73
PWM 5. This signal is controlled by PWM Generator 2.TTLOPWM5
GPIO port E bit 2.TTLI/OPE2
74
QEI module 1 phase B.TTLIPhB1
GPIO port E bit 3.TTLI/OPE3
75
QEI module 1 phase A.TTLIPhA1
CPU Mode bit 1. Input must be set to logic 0 (grounded); other
encodings reserved.
TTLICMOD1
76
GPIO port C bit 3.TTLI/OPC3
77
JTAG TDO and SWO.TTLOSWO
JTAG TDO and SWO.TTLOTDO
GPIO port C bit 2.TTLI/OPC2
78
JTAG TDI.TTLITDI
GPIO port C bit 1.TTLI/OPC1
79
JTAG TMS and SWDIO.TTLI/OSWDIO
JTAG TMS and SWDIO.TTLI/OTMS
GPIO port C bit 0.TTLI/OPC0
80
JTAG/SWD CLK.TTLISWCLK
JTAG/SWD CLK.TTLITCK
Positive supply for I/O and some logic.Power-VDD
81
Ground reference for logic and I/O pins.Power-GND
82
VCC of the Ethernet PHY.Power-VCCPHY
83
VCC of the Ethernet PHY.Power-VCCPHY
84
GND of the Ethernet PHY.Power-GNDPHY
85
GND of the Ethernet PHY.Power-GNDPHY
86
Ground reference for logic and I/O pins.Power-GND
87
Positive supply for most of the logic function, including the
processor core and most peripherals.
Power-VDD25
88
GPIO port B bit 7.TTLI/OPB7
89
JTAG TRST.TTLITRST
GPIO port B bit 6.TTLI/OPB6
90
Analog comparator 0 positive input.AnalogIC0+
721June 18, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S8962 Microcontroller
NRND: Not recommended for new designs.