Datasheet

Table 21-1. Signals by Pin Number (continued)
DescriptionBuffer Type
a
Pin TypePin NamePin Number
Positive supply for most of the logic function, including the
processor core and most peripherals.
Power-VDD25
38
Ground reference for logic and I/O pins.Power-GND
39
RXIP of the Ethernet PHY.AnalogIRXIP
40
12.4-kΩ resistor (1% precision) used internally for Ethernet PHY.AnalogIERBIAS
41
GND of the Ethernet PHY.Power-GNDPHY
42
TXOP of the Ethernet PHY.AnalogOTXOP
43
Positive supply for I/O and some logic.Power-VDD
44
Ground reference for logic and I/O pins.Power-GND
45
TXON of the Ethernet PHY.AnalogOTXON
46
GPIO port F bit 0.TTLI/OPF0
47
PWM 0. This signal is controlled by PWM Generator 0.TTLOPWM0
Main oscillator crystal input or an external clock reference input.AnalogIOSC0
48
Main oscillator crystal output. Leave unconnected when using a
single-ended clock source.
AnalogOOSC1
49
An external input that brings the processor out of Hibernate mode
when asserted.
TTLIWAKE
50
An open-drain output with internal pull-up that indicates the
processor is in Hibernate mode.
ODOHIB
51
Hibernation module oscillator crystal input or an external clock
reference input. Note that this is either a crystal or a 32.768-kHz
oscillator for the Hibernation module RTC.
AnalogIXOSC0
52
Hibernation module oscillator crystal output. Leave unconnected
when using a single-ended clock source.
AnalogOXOSC1
53
Ground reference for logic and I/O pins.Power-GND
54
Power source for the Hibernation module. It is normally connected
to the positive terminal of a battery and serves as the battery
backup/Hibernation module power-source supply.
Power-VBAT
55
Positive supply for I/O and some logic.Power-VDD
56
Ground reference for logic and I/O pins.Power-GND
57
MDIO of the Ethernet PHY.TTLI/OMDIO
58
GPIO port F bit 3.TTLI/OPF3
59
Ethernet LED 0.TTLOLED0
GPIO port F bit 2.TTLI/OPF2
60
Ethernet LED 1.TTLOLED1
GPIO port F bit 1.TTLI/OPF1
61
QEI module 1 index.TTLIIDX1
Positive supply for most of the logic function, including the
processor core and most peripherals.
Power-VDD25
62
Ground reference for logic and I/O pins.Power-GND
63
System reset input.TTLIRST
64
CPU Mode bit 0. Input must be set to logic 0 (grounded); other
encodings reserved.
TTLICMOD0
65
GPIO port B bit 0.TTLI/OPB0
66
PWM 2. This signal is controlled by PWM Generator 1.TTLOPWM2
June 18, 2012720
Texas Instruments-Production Data
Signal Tables
NRND: Not recommended for new designs.