Datasheet

Register 11: QEI Interrupt Status and Clear (QEIISC), offset 0x028
This register provides the current set of interrupt sources that are asserted to the controller. Bits set
to 1 indicate the latched events that have occurred; a zero bit indicates that the event in question
has not occurred. This is a R/W1C register; writing a 1 to a bit position clears the corresponding
interrupt reason.
QEI Interrupt Status and Clear (QEIISC)
QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x028
Type R/W1C, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
IntIndexIntTimer
IntDir
IntError
reserved
R/W1CR/W1CR/W1CR/W1CROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:4
Phase Error Interrupt
Indicates that a phase error was detected.
0R/W1CIntError3
Direction Change Interrupt
Indicates that the direction has changed.
0R/W1CIntDir2
Velocity Timer Expired Interrupt
Indicates that the velocity timer has expired.
0R/W1CIntTimer1
Index Pulse Interrupt
Indicates that the index pulse has occurred.
0R/W1CIntIndex0
715June 18, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S8962 Microcontroller
NRND: Not recommended for new designs.