Datasheet

Register 10: QEI Raw Interrupt Status (QEIRIS), offset 0x024
This register provides the current set of interrupt sources that are asserted, regardless of whether
they cause an interrupt to be asserted to the controller (this is set through the QEIINTEN register).
Bits set to 1 indicate the latched events that have occurred; a zero bit indicates that the event in
question has not occurred.
QEI Raw Interrupt Status (QEIRIS)
QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x024
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
IntIndexIntTimer
IntDir
IntError
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:4
Phase Error Detected
Indicates that a phase error was detected.
0ROIntError3
Direction Change Detected
Indicates that the direction has changed.
0ROIntDir2
Velocity Timer Expired
Indicates that the velocity timer has expired.
0ROIntTimer1
Index Pulse Asserted
Indicates that the index pulse has occurred.
0ROIntIndex0
June 18, 2012714
Texas Instruments-Production Data
Quadrature Encoder Interface (QEI)
NRND: Not recommended for new designs.