Datasheet

Register 9: QEI Interrupt Enable (QEIINTEN), offset 0x020
This register contains enables for each of the QEI module’s interrupts. An interrupt is asserted to
the controller if its corresponding bit in this register is set to 1.
QEI Interrupt Enable (QEIINTEN)
QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x020
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
IntIndexIntTimer
IntDir
IntError
reserved
R/WR/WR/WR/WROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:4
Phase Error Interrupt Enable
When 1, an interrupt occurs when a phase error is detected.
0R/WIntError3
Direction Change Interrupt Enable
When 1, an interrupt occurs when the direction changes.
0R/WIntDir2
Timer Expires Interrupt Enable
When 1, an interrupt occurs when the velocity timer expires.
0R/WIntTimer1
Index Pulse Detected Interrupt Enable
When 1, an interrupt occurs when the index pulse is detected.
0R/WIntIndex0
713June 18, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S8962 Microcontroller
NRND: Not recommended for new designs.