Datasheet

Figure 19-1. QEI Block Diagram
Quadrature
Encoder
Velocity
Predivider
Interrupt Control
QEIINTEN
QEIRIS
QEIISC
Position Integrator
QEIMAXPOS
QEIPOS
Velocity Accumulator
QEICOUNT
QEISPEED
Velocity Timer
QEILOAD
QEITIME
PhA
PhB
IDX
clk
dir
Interrupt
Control & Status
QEICTL
QEISTAT
19.2 Signal Description
Table 19-1 on page 699 and Table 19-2 on page 699 list the external signals of the QEI module and
describe the function of each. The QEI signals are alternate functions for some GPIO signals and
default to be GPIO signals at reset. The column in the table below titled "Pin Assignment" lists the
possible GPIO pin placements for these QEI signals. The AFSEL bit in the GPIO Alternate Function
Select (GPIOAFSEL) register (page 311) should be set to choose the QEI function. For more
information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 289.
Table 19-1. QEI Signals (100LQFP)
DescriptionBuffer Type
a
Pin TypePin NumberPin Name
QEI module 0 index.TTLI100IDX0
QEI module 1 index.TTLI61IDX1
QEI module 0 phase A.TTLI25PhA0
QEI module 1 phase A.TTLI75PhA1
QEI module 0 phase B.TTLI23PhB0
QEI module 1 phase B.TTLI74PhB1
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 19-2. QEI Signals (108BGA)
DescriptionBuffer Type
a
Pin TypePin NumberPin Name
QEI module 0 index.TTLIF1IDX0
QEI module 1 index.TTLIH12IDX1
QEI module 0 phase A.TTLIL1PhA0
QEI module 1 phase A.TTLIA12PhA1
699June 18, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S8962 Microcontroller
NRND: Not recommended for new designs.