Datasheet

These registers contain a value to be compared against the counter (PWM0CMPA controls the

PWM generator 0 block, and so on). When this value matches the counter, a pulse is output; this

can drive the generation of a PWM signal (via the PWMnGENA/PWMnGENB registers) or drive an

interrupt or ADC trigger (via the PWMnINTEN register). If the value of this register is greater than

the PWMnLOAD register (see page 685), then no pulse is ever output.

If the comparator A update mode is immediate (based on the CmpAUpd bit in the PWMnCTL register),

this 16-bit CompA value is used the next time the counter reaches zero. If the update mode is

synchronous, it is used the next time the counter reaches zero after a synchronous update has been

requested through the PWM Master Control (PWMCTL) register (see page 669). If this register is

rewritten before the actual update occurs, the previous value is never used and is lost.

PWM0 Compare A (PWM0CMPA)

Base 0x4002.8000

Offset 0x058

Type R/W, reset 0x0000.0000

16171819202122232425262728293031

reserved

ROROROROROROROROROROROROROROROROType

0000000000000000Reset

0123456789101112131415

CompA

R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType

0000000000000000Reset

DescriptionResetTypeNameBit/Field

Software should not rely on the value of a reserved bit. To provide

compatibility with future products, the value of a reserved bit should be

preserved across a read-modify-write operation.

0x00ROreserved31:16

Comparator A Value

The value to be compared against the counter.

0x00R/WCompA15:0

687June 18, 2012

Texas Instruments-Production Data

Stellaris

LM3S8962 Microcontroller

NRND: Not recommended for new designs.