Datasheet

Figure 18-2. PWM Module Block Diagram
PWMnCMPA
Comparators
PWMnCMPB
PWMnLOAD
Timer
PWMnCOUNT
PWMnDBCTL
Dead-Band
Generator
PWMnDBRISE
PWMnDBFALL
PWMnCTL
Control
PWM Clock
PWM Generator Block
Signal
Generator
PWMnGENA
PWMnGENB
PWMnINTEN
Interrupt and
Trigger
Generator
PWMnRIS
PWMnISC
Fault(s)
PWMn_A
PWMn_B
Interrupts /
Triggers
PWMn_Fault
cmp A
cmp B
zero
load
dir
PWMnFLTSRC0
Fault
Condition
PWMnMINFLTPER
PWMnFLTSEN
PWMnFLTSTAT0
18.2 Signal Description
Table 18-1 on page 661 and Table 18-2 on page 661 list the external signals of the PWM module and
describe the function of each. The PWM controller signals are alternate functions for some GPIO
signals and default to be GPIO signals at reset. The column in the table below titled "Pin Assignment"
lists the possible GPIO pin placements for these PWM signals. The AFSEL bit in the GPIO Alternate
Function Select (GPIOAFSEL) register (page 311) should be set to choose the PWM function. For
more information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 289.
Table 18-1. PWM Signals (100LQFP)
DescriptionBuffer Type
a
Pin TypePin NumberPin Name
PWM Fault.TTLI99Fault
PWM 0. This signal is controlled by PWM Generator 0.TTLO47PWM0
PWM 1. This signal is controlled by PWM Generator 0.TTLO18PWM1
PWM 2. This signal is controlled by PWM Generator 1.TTLO66PWM2
PWM 3. This signal is controlled by PWM Generator 1.TTLO67PWM3
PWM 4. This signal is controlled by PWM Generator 2.TTLO72PWM4
PWM 5. This signal is controlled by PWM Generator 2.TTLO73PWM5
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 18-2. PWM Signals (108BGA)
DescriptionBuffer Type
a
Pin TypePin NumberPin Name
PWM Fault.TTLIF2Fault
PWM 0. This signal is controlled by PWM Generator 0.TTLOM9PWM0
PWM 1. This signal is controlled by PWM Generator 0.TTLOK2PWM1
PWM 2. This signal is controlled by PWM Generator 1.TTLOE12PWM2
661June 18, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S8962 Microcontroller
NRND: Not recommended for new designs.