Datasheet

■ Flexible output control block with PWM output enable of each PWM signal
– PWM output enable of each PWM signal
– Optional output inversion of each PWM signal (polarity control)
– Optional fault handling for each PWM signal
– Synchronization of timers in the PWM generator blocks
– Interrupt status summary of the PWM generator blocks
■ Can initiate an ADC sample sequence
18.1 Block Diagram
Figure 18-1 on page 660 provides the Stellaris PWM module unit diagram and Figure 18-2 on page 661
provides a more detailed diagram of a Stellaris PWM generator. The LM3S8962 controller contains
three generator blocks (PWM0, PWM1, and PWM2) and generates six independent PWM signals
or three paired PWM signals with dead-band delays inserted.
Figure 18-1. PWM Unit Diagram
PWMINTEN
Interrupt
PWMRIS
PWMISC
PWMCTL
Control and
Status
PWMSYNC
PWMSTATUS
PWM
Generator 0
PWM
Generator 1
PWM
Generator 2
PWM 0
PWM 1
PWM 2
PWM 3
PWM 4
PWM 5
PWM
Output
Control
Logic
PWM Clock
System Clock
Interrupts
Triggers
PWM0_A
PWM0_B
PWM1_A
PWM1_B
PWM2_A
PWM2_B
PWM0_Fault
PWM1_Fault
PWM2_Fault
Fault
PWMENABLE
Output
PWMINVERT
PWMFAULT
June 18, 2012660
Texas Instruments-Production Data
Pulse Width Modulator (PWM)
NRND: Not recommended for new designs.