Datasheet

Register 24: Ethernet PHY Management Register 17 – Interrupt Control/Status
(MR17), address 0x11
This register provides the means for controlling and observing the events which trigger a PHY layer
interrupt in the MACRIS register. This register can also be used in a polling mode via the Media
Independent Interface as a means to observe key events within the PHY layer via one register
address. Bits 0 through 7 are status bits which are each set based on an event. These bits are
cleared after the register is read. Bits 8 through 15 of this register, when set, enable the corresponding
bit in the lower byte to signal a PHY layer interrupt in the MACRIS register.
Ethernet PHY Management Register 17 – Interrupt Control/Status (MR17)
Base 0x4004.8000
Address 0x11
Type R/W, reset 0x0000
0123456789101112131415
ANEGCOMP_INTRFAULT_INT
LSCHG_INTLPACK_INT
PDF_INTPRX_INT
RXER_INT
JABBER_INTANEGCOMP_IE
RFAULT_IELSCHG_IELPACK_IE
PDF_IEPRX_IERXER_IE
JABBER_IE
RCRCRCRCRCRCRCRCR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Jabber Interrupt Enable
When set, this bit enables system interrupts when a Jabber condition
is detected by the Ethernet Controller.
0R/WJABBER_IE15
Receive Error Interrupt Enable
When set, this bit enables system interrupts when a receive error is
detected by the Ethernet Controller.
0R/WRXER_IE14
Page Received Interrupt Enable
When set, this bit enables system interrupts when a new page is received
by the Ethernet Controller.
0R/WPRX_IE13
Parallel Detection Fault Interrupt Enable
When set, this bit enables system interrupts when a Parallel Detection
Fault is detected by the Ethernet Controller.
0R/WPDF_IE12
LP Acknowledge Interrupt Enable
When set, this bit enables system interrupts when FLP bursts are
received with the ACK bit in the MR5 register during auto-negotiation.
0R/WLPACK_IE11
Link Status Change Interrupt Enable
When set, this bit enables system interrupts when the link status changes
from OK to FAIL.
0R/WLSCHG_IE10
Remote Fault Interrupt Enable
When set, this bit enables system interrupts when a remote fault
condition is signaled by the link partner.
0R/WRFAULT_IE9
Auto-Negotiation Complete Interrupt Enable
When set, this bit enables system interrupts when the auto-negotiation
sequence has completed successfully.
0R/WANEGCOMP_IE8
Jabber Event Interrupt
When set, this bit indicates that a Jabber event has been detected by
the 10BASE-T circuitry.
0RCJABBER_INT7
641June 18, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S8962 Microcontroller
NRND: Not recommended for new designs.