Datasheet

Register 15: Ethernet MAC Timer Support (MACTS), offset 0x03C
This register enables software to enable highly precise timing on the transmission and reception of
frames. To enable this function, set the TSEN bit.
Ethernet MAC Timer Support (MACTS)
Base 0x4004.8000
Offset 0x03C
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TSENreserved
R/WROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000ROreserved31:1
Time Stamp Enable
When set, the TSEN bit multiplexes the TX and RX interrupts to the CCP
inputs of General-Purpose Timer 3.
0R/WTSEN0
16.7 MII Management Register Descriptions
The IEEE 802.3 standard specifies a register set for controlling and gathering status from the PHY
layer. The registers are collectively known as the MII Management registers. All addresses given
are absolute. Addresses not listed are reserved; these addresses should not be written to and any
data read should be ignored. Also see “Ethernet MAC Register Descriptions” on page 609.
June 18, 2012628
Texas Instruments-Production Data
Ethernet Controller
NRND: Not recommended for new designs.