Datasheet

Register 9: Ethernet MAC Management Control (MACMCTL), offset 0x020
This register enables software to control the transfer of data to and from the MII Management
registers in the Ethernet PHY layer. The address, name, type, reset configuration, and functional
description of each of these registers can be found in Table 16-4 on page 608 and in “MII Management
Register Descriptions” on page 628.
In order to initiate a read transaction from the MII Management registers, the WRITE bit must be
cleared during the same cycle that the START bit is set.
In order to initiate a write transaction to the MII Management registers, the WRITE bit must be set
during the same cycle that the START bit is set.
Ethernet MAC Management Control (MACMCTL)
Base 0x4004.8000
Offset 0x020
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
STARTWRITE
reserved
REGADRreserved
R/WR/WROR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.00ROreserved31:8
MII Register Address
The REGADR bit field represents the MII Management register address
for the next MII management interface transaction. Refer to
Table 16-4 on page 608 for the PHY register offsets.
Note that any address that is not valid in the register map should not be
written to and any data read should be ignored.
0x0R/WREGADR7:3
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved2
MII Register Transaction Type
The WRITE bit represents the operation of the next MII management
interface transaction. If WRITE is set, the next operation is a write; if
WRITE is clear, the next transaction is a read.
0R/WWRITE1
MII Register Transaction Enable
The START bit represents the initiation of the next MII management
interface transaction. When this bit is set, the MII register located at
REGADR is read (WRITE=0) or written (WRITE=1).
0R/WSTART0
June 18, 2012622
Texas Instruments-Production Data
Ethernet Controller
NRND: Not recommended for new designs.