Datasheet

Register 4: Ethernet MAC Transmit Control (MACTCTL), offset 0x00C
This register configures the transmitter and controls the frames that are transmitted.
Ethernet MAC Transmit Control (MACTCTL)
Base 0x4004.8000
Offset 0x00C
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TXENPADENCRC
reserved
DUPLEXreserved
R/WR/WR/WROR/WROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000ROreserved31:5
Enable Duplex Mode
When set, this bit enables Duplex mode, allowing simultaneous
transmission and reception.
0R/WDUPLEX4
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved3
Enable CRC Generation
When set this bit enables the automatic generation of the CRC and its
placement at the end of the packet. If this bit is clear, the frames placed
in the TX FIFO are sent exactly as they are written into the FIFO.
Note that this bit should generally be set.
0R/WCRC2
Enable Packet Padding
When set, this bit enables the automatic padding of packets that do not
meet the minimum frame size.
Note that this bit should generally be set.
0R/WPADEN1
Enable Transmitter
When set, this bit enables the transmitter. When this bit is clear, the
transmitter is disabled.
0R/WTXEN0
615June 18, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S8962 Microcontroller
NRND: Not recommended for new designs.