Datasheet

Register 3: Ethernet MAC Receive Control (MACRCTL), offset 0x008
This register configures the receiver and controls the types of frames that are received.
It is important to note that when the receiver is enabled, all valid frames with a broadcast address
of FF-FF-FF-FF-FF-FF in the Destination Address field are received and stored in the RX FIFO,
even if the AMUL bit is not set.
Ethernet MAC Receive Control (MACRCTL)
Base 0x4004.8000
Offset 0x008
Type R/W, reset 0x0000.0008
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RXENAMULPRMSBADCRCRSTFIFOreserved
R/WR/WR/WR/WR/WROROROROROROROROROROROType
0001000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000ROreserved31:5
Clear Receive FIFO
When set, this bit clears the receive FIFO. This should be done when
software initialization is performed.
It is recommended that the receiver be disabled (RXEN = 0), before a
reset is initiated (RSTFIFO = 1). This sequence flushes and resets the
RX FIFO.
This bit is automatically cleared when read.
0R/WRSTFIFO4
Enable Reject Bad CRC
When set, the BADCRC bit enables the rejection of frames with an
incorrectly calculated CRC. If a bad CRC is encountered, the RXER bit
in the MACRIS register is set and the receiver FIFO is reset.
1R/WBADCRC3
Enable Promiscuous Mode
When set, the PRMS bit enables Promiscuous mode, which accepts all
valid frames, regardless of the specified Destination Address.
0R/WPRMS2
Enable Multicast Frames
When set, the AMUL bit enables the reception of multicast frames.
0R/WAMUL1
Enable Receiver
When set the RXEN bit enables the Ethernet receiver. When this bit is
clear, the receiver is disabled and all frames are ignored.
0R/WRXEN0
June 18, 2012614
Texas Instruments-Production Data
Ethernet Controller
NRND: Not recommended for new designs.