Datasheet

Register 2: Ethernet MAC Interrupt Mask (MACIM), offset 0x004
This register allows software to enable/disable Ethernet MAC interrupts. Clearing a bit disables the
interrupt, while setting the bit enables it.
Ethernet MAC Interrupt Mask (MACIM)
Base 0x4004.8000
Offset 0x004
Type R/W, reset 0x0000.007F
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RXINTMTXERMTXEMPMFOVMRXERMMDINTMPHYINTMreserved
R/WR/WR/WR/WR/WR/WR/WROROROROROROROROROType
1111111000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.00ROreserved31:7
Mask PHY Interrupt
Clearing this bit masks the PHYINT bit in the MACRIS register from
being set.
1R/WPHYINTM6
Mask MII Transaction Complete
Clearing this bit masks the MDINT bit in the MACRIS register from being
set.
1R/WMDINTM5
Mask Receive Error
Clearing this bit masks the RXER bit in the MACRIS register from being
set.
1R/WRXERM4
Mask FIFO Overrun
Clearing this bit masks the FOV bit in the MACRIS register from being
set.
1R/WFOVM3
Mask Transmit FIFO Empty
Clearing this bit masks the TXEMP bit in the MACRIS register from being
set.
1R/WTXEMPM2
Mask Transmit Error
Clearing this bit masks the TXER bit in the MACRIS register from being
set.
1R/WTXERM1
Mask Packet Received
Clearing this bit masks the RXINT bit in the MACRIS register from being
set.
1R/WRXINTM0
613June 18, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S8962 Microcontroller
NRND: Not recommended for new designs.