Datasheet

4. Program the MACRCTL register to flush the receive FIFO and reject frames with bad FCS using
a value of 0x18.
5. Enable both the Transmitter and Receive by setting the LSB in both the MACTCTL and
MACRCTL registers.
6. To transmit a frame, write the frame into the TX FIFO using the Ethernet MAC Data (MACDATA)
register. Then set the NEWTX bit in the Ethernet Mac Transmission Request (MACTR) register
to initiate the transmit process. When the NEWTX bit has been cleared, the TX FIFO is available
for the next transmit frame.
7. To receive a frame, wait for the NPR field in the Ethernet MAC Number of Packets (MACNP)
register to be non-zero. Then begin reading the frame from the RX FIFO by using the MACDATA
register. To ensure that the entire packet is received, either use the DriverLib EthernetPacketGet()
API or compare the number of bytes received to the Length field from the frame to determine
when the packet has been completely read.
16.5 Ethernet Register Map
Table 16-4 on page 608 lists the Ethernet MAC registers. All addresses given are relative to the
Ethernet MAC base address of 0x4004.8000. Note that the Ethernet module clock must be enabled
before the registers can be programmed (see page 232). There must be a delay of 3 system clocks
after the Ethernet module clock is enabled before any Ethernet module registers are accessed.
The IEEE 802.3 standard specifies a register set for controlling and gathering status from the PHY
layer. The registers are collectively known as the MII Management registers and are detailed in
Section 22.2.4 of the IEEE 802.3 specification. Table 16-4 on page 608 also lists these MII
Management registers. All addresses given are absolute and are written directly to the REGADR field
of the Ethernet MAC Management Control (MACMCTL) register. The format of registers 0 to 15
are defined by the IEEE specification and are common to all PHY layer implementations. The only
variance allowed is for features that may or may not be supported by a specific PHY implementation.
Registers 16 to 31 are vendor-specific registers, used to support features that are specific to a
vendor's PHY implementation. Vendor-specific registers not listed are reserved.
Table 16-4. Ethernet Register Map
See
page
DescriptionResetTypeNameOffset
Ethernet MAC
610Ethernet MAC Raw Interrupt Status/Acknowledge0x0000.0000R/W1CMACRIS/MACIACK0x000
613Ethernet MAC Interrupt Mask0x0000.007FR/WMACIM0x004
614Ethernet MAC Receive Control0x0000.0008R/WMACRCTL0x008
615Ethernet MAC Transmit Control0x0000.0000R/WMACTCTL0x00C
616Ethernet MAC Data0x0000.0000R/WMACDATA0x010
618Ethernet MAC Individual Address 00x0000.0000R/WMACIA00x014
619Ethernet MAC Individual Address 10x0000.0000R/WMACIA10x018
620Ethernet MAC Threshold0x0000.003FR/WMACTHR0x01C
622Ethernet MAC Management Control0x0000.0000R/WMACMCTL0x020
June 18, 2012608
Texas Instruments-Production Data
Ethernet Controller
NRND: Not recommended for new designs.