Datasheet

Figure 16-4. Interface to an Ethernet Jack
6
5
8
4
2
3
1
7
1CT: 1
TX+
TX-
RX+
RX-
1CT: 1
Y+
Y
-
G+
G-
3
8
7
4
5
6
11
12
2
1
GL
G
R
9
10
NC
G
ND
P2
J
3
011G21DNL
R5
49.9
+3.3V
C13
0.0
1
UF
R4
49.9
R8
49.
9
R
9
49.
9
C4
0.1UF
+3.3V
C5
0.1UF
+3.3V
C7
10pF
C2
10pF
C3
10pF
R6
330
R3
10K
+3.3V
R7
330
+3.3V
+3.3V
PF2/LED1
PF3/LED0
C6
10pF
10/100BASE-T Ethernet Jack
+
3
.3
V
PF2/LED1
60
PF3/LED0
59
MDIO
58
TXON
46
TXOP
43
RXIP
40
RXIN
37
Stellaris
Microcontroller
The following isolation transformers have been tested and are known to successfully interface to
the Ethernet PHY layer.
■ Isolation Transformers
– TDK TLA-6T103
– Bel-Fuse S558-5999-46
– Halo TG22-3506ND
– Pulse PE-68515
– Valor ST6118
– YCL 20PMT04
■ Isolation transformers in low profile packages (0.100 in/2.5 mm or less)
– TDK TLA-6T118
– Halo TG110-S050
– PCA EPF8023G
■ Isolation transformers with integrated RJ45 connector
– TDK TLA-6T704
– Delta RJS-1A08T089A
■ Isolation transformers with integrated RJ45 connector, LEDs and termination resistors
– Pulse J0011D21B/E
– Pulse J3011G21DNL
16.4.2 Software Configuration
To use the Ethernet Controller, it must be enabled by setting the EPHY0 and EMAC0 bits in the
RCGC2 register (see page 232). The following steps can then be used to configure the Ethernet
Controller for basic operation.
1. Program the MACDIV register to obtain a 2.5 MHz clock (or less) on the internal MII. Assuming
a 20-MHz system clock, the MACDIV value should be 0x03 or greater.
2. Program the MACIA0 and MACIA1 register for address filtering.
3. Program the MACTCTL register for Auto CRC generation, padding, and full-duplex operation
using a value of 0x16.
607June 18, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S8962 Microcontroller
NRND: Not recommended for new designs.