Datasheet

and XTALNPHY pins. Alternatively, an external 25-MHz clock input can be connected to the XTALPPHY
pin. In this mode of operation, a crystal is not required and the XTALNPHY pin must be tied to ground.
16.3.3.2 Auto-Negotiation
The Ethernet Controller supports the auto-negotiation functions of Clause 28 of the IEEE 802.3
standard for 10/100 Mbps operation over copper wiring. This function is controlled via register
settings. The auto-negotiation function is turned on by default, and the ANEGEN bit in the Ethernet
PHY Management Register 0 - Control (MR0) is set after reset. Software can disable the
auto-negotiation function by clearing the ANEGEN bit. The contents of the Ethernet PHY Management
Register - Auto-Negotiation Advertisement (MR4) are reflected to the Ethernet Controller’s link
partner during auto-negotiation via fast-link pulse coding.
Once auto-negotiation is complete, the DPLX and RATE bits in the Ethernet PHY Management
Register 18 - Diagnostic (MR18) register reflect the actual speed and duplex condition. If
auto-negotiation fails to establish a link for any reason, the ANEGF bit in the MR18 register reflects
this and auto-negotiation restarts from the beginning. Setting the RANEG bit in the MR0 register also
causes auto-negotiation to restart.
16.3.3.3 Polarity Correction
The Ethernet Controller is capable of either automatic or manual polarity reversal for 10BASE-T
and auto-negotiation functions. Bits 4 and 5 (RVSPOL and APOL) in the Ethernet PHY Management
Register 16 - Vendor-Specific (MR16) control this feature. The default is automatic mode, where
APOL is clear and RVSPOL indicates if the detection circuitry has inverted the input signal. To enter
manual mode, APOL should be set. In manual mode RVSPOL controls the signal polarity.
16.3.3.4 MDI/MDI-X Configuration
The Ethernet Controller supports the MDI/MDI-X configuration as defined in IEEE 802.3-2002
specification. The MDI/MDI-X configuration eliminates the need for cross-over cables when connecting
to another device, such as a hub. The algorithm is controlled via settings in the Ethernet PHY
Management Register 24 - MDI/MIDIX Control (MR24). Refer to page 646 for additional details
about these settings.
16.3.3.5 Power Management
The PHY has two power-saving modes:
■ Power-Down
■ Receive Power Management
Power-down mode is activated by setting the PWRDN bit in the MR0 register. When the PHY is in
power-down mode, it consumes minimum power. While in the power-down state, the Ethernet
Controller still responds to management transactions.
Receive power management (RXCC mode) is activated by setting the RXCC bit in the MR16 register.
In this mode of operation, the adaptive equalizer, the clock recovery phase lock loop (PLL), and all
other receive circuitry are powered down. As soon as a valid signal is detected, all circuits are
automatically powered up to resume normal operation. Note that the RXCC mode is not supported
during 10BASE-T operation.
605June 18, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S8962 Microcontroller
NRND: Not recommended for new designs.