Datasheet

Table 16-3. TX & RX FIFO Organization
RX FIFO (Read)TX FIFO (Write)Word Bit FieldsFIFO Word Read/Write
Sequence
Frame Length Least
Significant Byte
Data Length Least Significant
Byte
7:01st
Frame Length Most Significant
Byte
Data Length Most Significant
Byte
15:8
DA oct 123:16
DA oct 231:24
DA oct 37:02nd
DA oct 415:8
DA oct 523:16
DA oct 631:24
SA oct 17:03rd
SA oct 215:8
SA oct 323:16
SA oct 431:24
SA oct 57:04th
SA oct 615:8
Len/Type Most Significant Byte23:16
Len/Type Least Significant Byte31:24
data oct n7:05th to nth
data oct n+115:8
data oct n+223:16
data oct n+331:24
FCS 17:0last
FCS 215:8
FCS 323:16
FCS 431:24
Note: If the CRC bit in the MACTCTL register is clear, the FCS bytes must be written with the
correct CRC. If the CRC bit is set, the Ethernet Controller automatically writes the FCS bytes.
16.3.1.3 Ethernet Transmission Options
At the MAC layer, the transmitter can be configured for both full-duplex and half-duplex operation
by using the DUPLEX bit in the MACTCTL register.
The Ethernet Controller automatically generates and inserts the Frame Check Sequence (FCS) at
the end of the transmit frame when the CRC bit in the MACTCTL register is set. However, for test
purposes, this feature can be disabled in order to generate a frame with an invalid CRC by clearing
the CRC bit.
The IEEE 802.3 specification requires that the Ethernet frame payload section be a minimum of 46
bytes. The Ethernet Controller automatically pads the data section if the payload data section loaded
into the FIFO is less than the minimum 46 bytes when the PADEN bit in the MACTCTL register is
set. This feature can be disabled by clearing the PADEN bit.
The transmitter must be enabled by setting the TXEN bit in the TCTL register.
603June 18, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S8962 Microcontroller
NRND: Not recommended for new designs.