Datasheet

9.3.2 32-Bit Timer Operating Modes ...................................................................................... 338
9.3.3 16-Bit Timer Operating Modes ...................................................................................... 340
9.4 Initialization and Configuration ..................................................................................... 344
9.4.1 32-Bit One-Shot/Periodic Timer Mode ........................................................................... 344
9.4.2 32-Bit Real-Time Clock (RTC) Mode ............................................................................. 345
9.4.3 16-Bit One-Shot/Periodic Timer Mode ........................................................................... 345
9.4.4 16-Bit Input Edge Count Mode ..................................................................................... 346
9.4.5 16-Bit Input Edge Timing Mode .................................................................................... 346
9.4.6 16-Bit PWM Mode ....................................................................................................... 347
9.5 Register Map .............................................................................................................. 347
9.6 Register Descriptions .................................................................................................. 348
10 Watchdog Timer ................................................................................................... 373
10.1 Block Diagram ............................................................................................................ 374
10.2 Functional Description ................................................................................................. 374
10.3 Initialization and Configuration ..................................................................................... 375
10.4 Register Map .............................................................................................................. 375
10.5 Register Descriptions .................................................................................................. 376
11 Analog-to-Digital Converter (ADC) ..................................................................... 397
11.1 Block Diagram ............................................................................................................ 397
11.2 Signal Description ....................................................................................................... 398
11.3 Functional Description ................................................................................................. 399
11.3.1 Sample Sequencers .................................................................................................... 399
11.3.2 Module Control ............................................................................................................ 400
11.3.3 Hardware Sample Averaging Circuit ............................................................................. 400
11.3.4 Analog-to-Digital Converter .......................................................................................... 401
11.3.5 Differential Sampling ................................................................................................... 401
11.3.6 Test Modes ................................................................................................................. 403
11.3.7 Internal Temperature Sensor ........................................................................................ 403
11.4 Initialization and Configuration ..................................................................................... 404
11.4.1 Module Initialization ..................................................................................................... 404
11.4.2 Sample Sequencer Configuration ................................................................................. 404
11.5 Register Map .............................................................................................................. 405
11.6 Register Descriptions .................................................................................................. 406
12 Universal Asynchronous Receivers/Transmitters (UARTs) ............................. 434
12.1 Block Diagram ............................................................................................................ 435
12.2 Signal Description ....................................................................................................... 435
12.3 Functional Description ................................................................................................. 436
12.3.1 Transmit/Receive Logic ............................................................................................... 436
12.3.2 Baud-Rate Generation ................................................................................................. 437
12.3.3 Data Transmission ...................................................................................................... 437
12.3.4 Serial IR (SIR) ............................................................................................................. 438
12.3.5 FIFO Operation ........................................................................................................... 439
12.3.6 Interrupts .................................................................................................................... 439
12.3.7 Loopback Operation .................................................................................................... 440
12.3.8 IrDA SIR block ............................................................................................................ 440
12.4 Initialization and Configuration ..................................................................................... 440
12.5 Register Map .............................................................................................................. 441
12.6 Register Descriptions .................................................................................................. 442
June 18, 20126
Texas Instruments-Production Data
Table of Contents
NRND: Not recommended for new designs.