Datasheet

tPhase2 = 4 * t
q
\\tPhase2 = tPhase1
tTSeg1 = tProp + tPhase1
tTSeg1 = (1 * t
q
) + (4 * t
q
)
tTSeg1 = 5 * t
q
tTSeg2 = tPhase2
tTSeg2 = (Information Processing Time + 4) * t
q
tTSeg2 = 4 * t
q
\\Assumes IPT=0
tSJW = 4 * t
q
\\Least of 4, Phase1, and Phase2
= TSeg2 -1
= 4-1
= 3
TSEG2
= TSeg1 -1
= 5-1
= 4
TSEG1
= SJW -1
= 4-1
= 3
SJW
= Baud rate prescaler - 1
= 8-1
= 7
BRP
The final value programmed into the CANBIT register = 0x34C7.
15.4 Register Map
Table 15-5 on page 570 lists the registers. All addresses given are relative to the CAN base address
of:
■ CAN0: 0x4004.0000
Note that the CAN module clock must be enabled before the registers can be programmed (see
page 217). There must be a delay of 3 system clocks after the CAN module clock is enabled before
any CAN module registers are accessed.
Table 15-5. CAN Register Map
See
page
DescriptionResetTypeNameOffset
573CAN Control0x0000.0001R/WCANCTL0x000
575CAN Status0x0000.0000R/WCANSTS0x004
577CAN Error Counter0x0000.0000ROCANERR0x008
578CAN Bit Timing0x0000.2301R/WCANBIT0x00C
579CAN Interrupt0x0000.0000ROCANINT0x010
580CAN Test0x0000.0000R/WCANTST0x014
582CAN Baud Rate Prescaler Extension0x0000.0000R/WCANBRPE0x018
June 18, 2012570
Texas Instruments-Production Data
Controller Area Network (CAN) Module
NRND: Not recommended for new designs.