Datasheet

Register 14: I
2
C Slave Raw Interrupt Status (I2CSRIS), offset 0x810
This register specifies whether an interrupt is pending.
I2C Slave Raw Interrupt Status (I2CSRIS)
I2C 0 base: 0x4002.0000
Offset 0x810
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
DATARISreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:1
Data Raw Interrupt Status
This bit specifies the raw interrupt state for data received and data
requested (prior to masking) of the I
2
C slave block. If set, an interrupt
is pending; otherwise, an interrupt is not pending.
0RODATARIS0
June 18, 2012548
Texas Instruments-Production Data
Inter-Integrated Circuit (I
2
C) Interface
NRND: Not recommended for new designs.