Datasheet

Register 11: I
2
C Slave Control/Status (I2CSCSR), offset 0x804
This register accesses one control bit when written, and three status bits when read.
The read-only Status register consists of three bits: the FBR, RREQ, and TREQ bits. The First
Byte Received (FBR) bit is set only after the Stellaris device detects its own slave address and
receives the first data byte from the I
2
C master. The Receive Request (RREQ) bit indicates that
the Stellaris I
2
C device has received a data byte from an I
2
C master. Read one data byte from the
I
2
C Slave Data (I2CSDR) register to clear the RREQ bit. The Transmit Request (TREQ) bit
indicates that the Stellaris I
2
C device is addressed as a Slave Transmitter. Write one data byte into
the I
2
C Slave Data (I2CSDR) register to clear the TREQ bit.
The write-only Control register consists of one bit: the DA bit. The DA bit enables and disables the
Stellaris I
2
C slave operation.
Reads
I2C Slave Control/Status (I2CSCSR)
I2C 0 base: 0x4002.0000
Offset 0x804
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RREQTREQFBRreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:3
First Byte Received
Indicates that the first byte following the slave’s own address is received.
This bit is only valid when the RREQ bit is set, and is automatically cleared
when data has been read from the I2CSDR register.
Note: This bit is not used for slave transmit operations.
0ROFBR2
Transmit Request
This bit specifies the state of the I
2
C slave with regards to outstanding
transmit requests. If set, the I
2
C unit has been addressed as a slave
transmitter and uses clock stretching to delay the master until data has
been written to the I2CSDR register. Otherwise, there is no outstanding
transmit request.
0ROTREQ1
Receive Request
This bit specifies the status of the I
2
C slave with regards to outstanding
receive requests. If set, the I
2
C unit has outstanding receive data from
the I
2
C master and uses clock stretching to delay the master until the
data has been read from the I2CSDR register. Otherwise, no receive
data is outstanding.
0RORREQ0
June 18, 2012544
Texas Instruments-Production Data
Inter-Integrated Circuit (I
2
C) Interface
NRND: Not recommended for new designs.