Datasheet

DescriptionResetTypeNameBit/Field
Acknowledge Data
This bit specifies the result of the last data operation. If set, the
transmitted data was not acknowledged; otherwise, the data was
acknowledged.
0RODATACK3
Acknowledge Address
This bit specifies the result of the last address operation. If set, the
transmitted address was not acknowledged; otherwise, the address was
acknowledged.
0ROADRACK2
Error
This bit specifies the result of the last bus operation. If set, an error
occurred on the last operation; otherwise, no error was detected. The
error can be from the slave address not being acknowledged or the
transmit data not being acknowledged.
0ROERROR1
I
2
C Busy
This bit specifies the state of the controller. If set, the controller is busy;
otherwise, the controller is idle. When the BUSY bit is set, the other status
bits are not valid.
0ROBUSY0
Writes
I2C Master Control/Status (I2CMCS)
I2C 0 base: 0x4002.0000
Offset 0x004
Type WO, reset 0x0000.0000
16171819202122232425262728293031
reserved
WOWOWOWOWOWOWOWOWOWOWOWOWOWOWOWOType
0000000000000000Reset
0123456789101112131415
RUNSTARTSTOPACKreserved
WOWOWOWOWOWOWOWOWOWOWOWOWOWOWOWOType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00WOreserved31:4
Data Acknowledge Enable
When set, causes received data byte to be acknowledged automatically
by the master. See field decoding in Table 14-5 on page 533.
0WOACK3
Generate STOP
When set, causes the generation of the STOP condition. See field
decoding in Table 14-5 on page 533.
0WOSTOP2
Generate START
When set, causes the generation of a START or repeated START
condition. See field decoding in Table 14-5 on page 533.
0WOSTART1
June 18, 2012532
Texas Instruments-Production Data
Inter-Integrated Circuit (I
2
C) Interface
NRND: Not recommended for new designs.