Datasheet

Figure 14-2. I
2
C Bus Configuration
R
PUP
Stellaris
TM
I2CSCL I2CSDA
R
PUP
3rd Party Device
with I
2
C Interface
SCL SDA
I
2
C Bus
SCL
SDA
3rd Party Device
with I
2
C Interface
SCL SDA
14.3.1 I
2
C Bus Functional Overview
The I
2
C bus uses only two signals: SDA and SCL, named I2CSDA and I2CSCL on Stellaris
microcontrollers. SDA is the bi-directional serial data line and SCL is the bi-directional serial clock
line. The bus is considered idle when both lines are High.
Every transaction on the I
2
C bus is nine bits long, consisting of eight data bits and a single
acknowledge bit. The number of bytes per transfer (defined as the time between a valid START
and STOP condition, described in “START and STOP Conditions” on page 516) is unrestricted, but
each byte has to be followed by an acknowledge bit, and data must be transferred MSB first. When
a receiver cannot receive another complete byte, it can hold the clock line SCL Low and force the
transmitter into a wait state. The data transfer continues when the receiver releases the clock SCL.
14.3.1.1 START and STOP Conditions
The protocol of the I
2
C bus defines two states to begin and end a transaction: START and STOP.
A High-to-Low transition on the SDA line while the SCL is High is defined as a START condition,
and a Low-to-High transition on the SDA line while SCL is High is defined as a STOP condition.
The bus is considered busy after a START condition and free after a STOP condition. See Figure
14-3 on page 516.
Figure 14-3. START and STOP Conditions
START
condition
SD
A
SCL
STOP
condition
SD
A
SCL
14.3.1.2 Data Format with 7-Bit Address
Data transfers follow the format shown in Figure 14-4 on page 517. After the START condition, a
slave address is sent. This address is 7-bits long followed by an eighth bit, which is a data direction
bit (R/S bit in the I2CMSA register). A zero indicates a transmit operation (send), and a one indicates
a request for data (receive). A data transfer is always terminated by a STOP condition generated
by the master, however, a master can initiate communications with another device on the bus by
generating a repeated START condition and addressing another slave without first generating a
STOP condition. Various combinations of receive/send formats are then possible within a single
transfer.
June 18, 2012516
Texas Instruments-Production Data
Inter-Integrated Circuit (I
2
C) Interface
NRND: Not recommended for new designs.