Datasheet

Register 9: SSI Interrupt Clear (SSIICR), offset 0x020
The SSIICR register is the interrupt clear register. On a write of 1, the corresponding interrupt is
cleared. A write of 0 has no effect.
SSI Interrupt Clear (SSIICR)
SSI0 base: 0x4000.8000
Offset 0x020
Type W1C, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RORICRTICreserved
W1CW1CROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:2
SSI Receive Time-Out Interrupt Clear
The RTIC values are defined as follows:
DescriptionValue
No effect on interrupt.0
Clears interrupt.1
0W1CRTIC1
SSI Receive Overrun Interrupt Clear
The RORIC values are defined as follows:
DescriptionValue
No effect on interrupt.0
Clears interrupt.1
0W1CRORIC0
501June 18, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S8962 Microcontroller
NRND: Not recommended for new designs.