Datasheet

■ 1 Mbps bit rate
■ 8 data bits
Assuming the system clock is 20 MHz, the bit rate calculation would be:
FSSIClk = FSysClk / (CPSDVSR * (1 + SCR))
1x106 = 20x106 / (CPSDVSR * (1 + SCR))
In this case, if CPSDVSR=2, SCR must be 9.
The configuration sequence would be as follows:
1. Ensure that the SSE bit in the SSICR1 register is disabled.
2. Write the SSICR1 register with a value of 0x0000.0000.
3. Write the SSICPSR register with a value of 0x0000.0002.
4. Write the SSICR0 register with a value of 0x0000.09C7.
5. The SSI is then enabled by setting the SSE bit in the SSICR1 register to 1.
13.5 Register Map
Table 13-3 on page 487 lists the SSI registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that SSI module’s base address:
■ SSI0: 0x4000.8000
Note that the SSI module clock must be enabled before the registers can be programmed (see
page 223). There must be a delay of 3 system clocks after the SSI module clock is enabled before
any SSI module registers are accessed.
Note: The SSI must be disabled (see the SSE bit in the SSICR1 register) before any of the control
registers are reprogrammed.
Table 13-3. SSI Register Map
See
page
DescriptionResetTypeNameOffset
489SSI Control 00x0000.0000R/WSSICR00x000
491SSI Control 10x0000.0000R/WSSICR10x004
493SSI Data0x0000.0000R/WSSIDR0x008
494SSI Status0x0000.0003ROSSISR0x00C
496SSI Clock Prescale0x0000.0000R/WSSICPSR0x010
497SSI Interrupt Mask0x0000.0000R/WSSIIM0x014
499SSI Raw Interrupt Status0x0000.0008ROSSIRIS0x018
500SSI Masked Interrupt Status0x0000.0000ROSSIMIS0x01C
501SSI Interrupt Clear0x0000.0000W1CSSIICR0x020
487June 18, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S8962 Microcontroller
NRND: Not recommended for new designs.