Datasheet

Table 12-1. UART Signals (100LQFP) (continued)
DescriptionBuffer Type
a
Pin TypePin NumberPin Name
UART module 1 transmit. When in IrDA mode, this signal has
IrDA modulation.
TTLO13U1Tx
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 12-2. UART Signals (108BGA)
DescriptionBuffer Type
a
Pin TypePin NumberPin Name
UART module 0 receive. When in IrDA mode, this signal has
IrDA modulation.
TTLIL3U0Rx
UART module 0 transmit. When in IrDA mode, this signal has
IrDA modulation.
TTLOM3U0Tx
UART module 1 receive. When in IrDA mode, this signal has
IrDA modulation.
TTLIH2U1Rx
UART module 1 transmit. When in IrDA mode, this signal has
IrDA modulation.
TTLOH1U1Tx
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
12.3 Functional Description
Each Stellaris UART performs the functions of parallel-to-serial and serial-to-parallel conversions.
It is similar in functionality to a 16C550 UART, but is not register compatible.
The UART is configured for transmit and/or receive via the TXE and RXE bits of the UART Control
(UARTCTL) register (see page 454). Transmit and receive are both enabled out of reset. Before any
control registers are programmed, the UART must be disabled by clearing the UARTEN bit in
UARTCTL. If the UART is disabled during a TX or RX operation, the current transaction is completed
prior to the UART stopping.
The UART peripheral also includes a serial IR (SIR) encoder/decoder block that can be connected
to an infrared transceiver to implement an IrDA SIR physical layer. The SIR function is programmed
using the UARTCTL register.
12.3.1 Transmit/Receive Logic
The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO.
The control logic outputs the serial bit stream beginning with a start bit, and followed by the data
bits (LSB first), parity bit, and the stop bits according to the programmed configuration in the control
registers. See Figure 12-2 on page 436 for details.
The receive logic performs serial-to-parallel conversion on the received bit stream after a valid start
pulse has been detected. Overrun, parity, frame error checking, and line-break detection are also
performed, and their status accompanies the data that is written to the receive FIFO.
Figure 12-2. UART Character Frame
1
0
5-8 data bits
LSB
MSB
Parity bit
if enabled
1-2
stop bits
UnTX
n
Start
June 18, 2012436
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
NRND: Not recommended for new designs.