Datasheet

Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004
This register shows the status of the raw interrupt signal of each sample sequencer. These bits may
be polled by software to look for interrupt conditions without having to generate controller interrupts.
ADC Raw Interrupt Status (ADCRIS)
Base 0x4003.8000
Offset 0x004
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
INR0INR1INR2INR3reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x000ROreserved31:4
SS3 Raw Interrupt Status
This bit is set by hardware when a sample with its respective
ADCSSCTL3 IE bit has completed conversion. This bit is cleared by
setting the IN3 bit in the ADCISC register.
0ROINR33
SS2 Raw Interrupt Status
This bit is set by hardware when a sample with its respective
ADCSSCTL2 IE bit has completed conversion. This bit is cleared by
setting the IN2 bit in the ADCISC register.
0ROINR22
SS1 Raw Interrupt Status
This bit is set by hardware when a sample with its respective
ADCSSCTL1 IE bit has completed conversion. This bit is cleared by
setting the IN1 bit in the ADCISC register.
0ROINR11
SS0 Raw Interrupt Status
This bit is set by hardware when a sample with its respective
ADCSSCTL0 IE bit has completed conversion. This bit is cleared by
setting the IN30 bit in the ADCISC register.
0ROINR00
June 18, 2012408
Texas Instruments-Production Data
Analog-to-Digital Converter (ADC)
NRND: Not recommended for new designs.