Datasheet
4. For each sample in the sample sequence, configure the sample control bits in the corresponding
nibble in the ADCSSCTLn register. When programming the last nibble, ensure that the END bit
is set. Failure to set the END bit causes unpredictable behavior.
5. If interrupts are to be used, write a 1 to the corresponding MASK bit in the ADCIM register.
6. Enable the sample sequencer logic by writing a 1 to the corresponding ASENn bit in the
ADCACTSS register.
11.5 Register Map
Table 11-5 on page 405 lists the ADC registers. The offset listed is a hexadecimal increment to the
register’s address, relative to the ADC base address of 0x4003.8000.
Note that the ADC module clock must be enabled before the registers can be programmed (see
page 217). There must be a delay of 3 system clocks after the ADC module clock is enabled before
any ADC module registers are accessed.
Table 11-5. ADC Register Map
See
page
DescriptionResetTypeNameOffset
407ADC Active Sample Sequencer0x0000.0000R/WADCACTSS0x000
408ADC Raw Interrupt Status0x0000.0000ROADCRIS0x004
409ADC Interrupt Mask0x0000.0000R/WADCIM0x008
410ADC Interrupt Status and Clear0x0000.0000R/W1CADCISC0x00C
411ADC Overflow Status0x0000.0000R/W1CADCOSTAT0x010
412ADC Event Multiplexer Select0x0000.0000R/WADCEMUX0x014
416ADC Underflow Status0x0000.0000R/W1CADCUSTAT0x018
417ADC Sample Sequencer Priority0x0000.3210R/WADCSSPRI0x020
419ADC Processor Sample Sequence Initiate-WOADCPSSI0x028
420ADC Sample Averaging Control0x0000.0000R/WADCSAC0x030
421ADC Sample Sequence Input Multiplexer Select 00x0000.0000R/WADCSSMUX00x040
423ADC Sample Sequence Control 00x0000.0000R/WADCSSCTL00x044
426ADC Sample Sequence Result FIFO 0-ROADCSSFIFO00x048
427ADC Sample Sequence FIFO 0 Status0x0000.0100ROADCSSFSTAT00x04C
428ADC Sample Sequence Input Multiplexer Select 10x0000.0000R/WADCSSMUX10x060
429ADC Sample Sequence Control 10x0000.0000R/WADCSSCTL10x064
426ADC Sample Sequence Result FIFO 1-ROADCSSFIFO10x068
427ADC Sample Sequence FIFO 1 Status0x0000.0100ROADCSSFSTAT10x06C
428ADC Sample Sequence Input Multiplexer Select 20x0000.0000R/WADCSSMUX20x080
429ADC Sample Sequence Control 20x0000.0000R/WADCSSCTL20x084
426ADC Sample Sequence Result FIFO 2-ROADCSSFIFO20x088
405June 18, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S8962 Microcontroller
NRND: Not recommended for new designs.