Datasheet

2.5.4 Vector Table .................................................................................................................. 87
2.5.5 Exception Priorities ....................................................................................................... 88
2.5.6 Interrupt Priority Grouping .............................................................................................. 89
2.5.7 Exception Entry and Return ........................................................................................... 89
2.6 Fault Handling .............................................................................................................. 91
2.6.1 Fault Types ................................................................................................................... 92
2.6.2 Fault Escalation and Hard Faults .................................................................................... 92
2.6.3 Fault Status Registers and Fault Address Registers ........................................................ 93
2.6.4 Lockup ......................................................................................................................... 93
2.7 Power Management ...................................................................................................... 93
2.7.1 Entering Sleep Modes ................................................................................................... 94
2.7.2 Wake Up from Sleep Mode ............................................................................................ 94
2.8 Instruction Set Summary ............................................................................................... 95
3 Cortex-M3 Peripherals ........................................................................................... 98
3.1 Functional Description ................................................................................................... 98
3.1.1 System Timer (SysTick) ................................................................................................. 98
3.1.2 Nested Vectored Interrupt Controller (NVIC) .................................................................... 99
3.1.3 System Control Block (SCB) ........................................................................................ 101
3.1.4 Memory Protection Unit (MPU) ..................................................................................... 101
3.2 Register Map .............................................................................................................. 106
3.3 System Timer (SysTick) Register Descriptions .............................................................. 108
3.4 NVIC Register Descriptions .......................................................................................... 112
3.5 System Control Block (SCB) Register Descriptions ........................................................ 125
3.6 Memory Protection Unit (MPU) Register Descriptions .................................................... 152
4 JTAG Interface ...................................................................................................... 162
4.1 Block Diagram ............................................................................................................ 163
4.2 Signal Description ....................................................................................................... 163
4.3 Functional Description ................................................................................................. 164
4.3.1 JTAG Interface Pins ..................................................................................................... 164
4.3.2 JTAG TAP Controller ................................................................................................... 166
4.3.3 Shift Registers ............................................................................................................ 167
4.3.4 Operational Considerations .......................................................................................... 167
4.4 Initialization and Configuration ..................................................................................... 170
4.5 Register Descriptions .................................................................................................. 170
4.5.1 Instruction Register (IR) ............................................................................................... 170
4.5.2 Data Registers ............................................................................................................ 173
5 System Control ..................................................................................................... 175
5.1 Signal Description ....................................................................................................... 175
5.2 Functional Description ................................................................................................. 175
5.2.1 Device Identification .................................................................................................... 176
5.2.2 Reset Control .............................................................................................................. 176
5.2.3 Power Control ............................................................................................................. 180
5.2.4 Clock Control .............................................................................................................. 181
5.2.5 System Control ........................................................................................................... 186
5.3 Initialization and Configuration ..................................................................................... 187
5.4 Register Map .............................................................................................................. 188
5.5 Register Descriptions .................................................................................................. 189
June 18, 20124
Texas Instruments-Production Data
Table of Contents
NRND: Not recommended for new designs.