Datasheet

This register is used to load the starting count value into the timer. When GPTM is configured to

one of the 32-bit modes, GPTMTAILR appears as a 32-bit register (the upper 16-bits correspond

to the contents of the GPTM TimerB Interval Load (GPTMTBILR) register). In 16-bit mode, the

upper 16 bits of this register read as 0s and have no effect on the state of GPTMTBILR.

GPTM TimerA Interval Load (GPTMTAILR)

Timer0 base: 0x4003.0000

Timer1 base: 0x4003.1000

Timer2 base: 0x4003.2000

Timer3 base: 0x4003.3000

Offset 0x028

Type R/W, reset 0xFFFF.FFFF

16171819202122232425262728293031

TAILRH

R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType

1111111111111111Reset

0123456789101112131415

TAILRL

R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType

1111111111111111Reset

DescriptionResetTypeNameBit/Field

GPTM TimerA Interval Load Register High

When configured for 32-bit mode via the GPTMCFG register, the GPTM

TimerB Interval Load (GPTMTBILR) register loads this value on a

write. A read returns the current value of GPTMTBILR.

In 16-bit mode, this field reads as 0 and does not have an effect on the

state of GPTMTBILR.

0xFFFFR/WTAILRH31:16

GPTM TimerA Interval Load Register Low

For both 16- and 32-bit modes, writing this field loads the counter for

TimerA. A read returns the current value of GPTMTAILR.

0xFFFFR/WTAILRL15:0

363June 18, 2012

Texas Instruments-Production Data

Stellaris

LM3S8962 Microcontroller

NRND: Not recommended for new designs.