Datasheet

Register 4: GPTM Control (GPTMCTL), offset 0x00C
This register is used alongside the GPTMCFG and GMTMTnMR registers to fine-tune the timer
configuration, and to enable other features such as timer stall and the output trigger. The output
trigger can be used to initiate transfers on the ADC module.
GPTM Control (GPTMCTL)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x00C
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TAENTASTALLTAEVENTRTCENTAOTETAPWML
reserved
TBENTBSTALLTBEVENT
reserved
TBOTETBPWML
reserved
R/WR/WR/WR/WR/WR/WR/WROR/WR/WR/WR/WROR/WR/WROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:15
GPTM TimerB PWM Output Level
The TBPWML values are defined as follows:
DescriptionValue
Output is unaffected.0
Output is inverted.1
0R/WTBPWML14
GPTM TimerB Output Trigger Enable
The TBOTE values are defined as follows:
DescriptionValue
The output TimerB ADC trigger is disabled.0
The output TimerB ADC trigger is enabled.1
In addition, the ADC must be enabled and the timer selected as a trigger
source with the EMn bit in the ADCEMUX register (see page 412).
0R/WTBOTE13
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved12
June 18, 2012354
Texas Instruments-Production Data
General-Purpose Timers
NRND: Not recommended for new designs.