Datasheet

Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008
This register configures the GPTM based on the configuration selected in the GPTMCFG register.
When in 16-bit PWM mode, set the TBAMS bit to 0x1, the TBCMR bit to 0x0, and the TBMR field to
0x2.
GPTM TimerB Mode (GPTMTBMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x008
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TBMRTBCMRTBAMSreserved
R/WR/WR/WR/WROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:4
GPTM TimerB Alternate Mode Select
The TBAMS values are defined as follows:
DescriptionValue
Capture mode is enabled.0
PWM mode is enabled.1
Note: To enable PWM mode, you must also clear the TBCMR
bit and set the TBMR field to 0x2.
0R/WTBAMS3
GPTM TimerB Capture Mode
The TBCMR values are defined as follows:
DescriptionValue
Edge-Count mode0
Edge-Time mode1
0R/WTBCMR2
June 18, 2012352
Texas Instruments-Production Data
General-Purpose Timers
NRND: Not recommended for new designs.