Datasheet

8.2.6 Identification
The identification registers configured at reset allow software to detect and identify the module as
a GPIO block. The identification registers include the GPIOPeriphID0-GPIOPeriphID7 registers as
well as the GPIOPCellID0-GPIOPCellID3 registers.
8.3 Initialization and Configuration
To use the GPIO, the peripheral clock must be enabled by setting the appropriate GPIO Port bit
field (GPIOn) in the RCGC2 register.
On reset, all GPIO pins (except for the five JTAG pins) are configured out of reset to be undriven
(tristate): GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0. Table 8-6 on page 298
shows all possible configurations of the GPIO pads and the control register settings required to
achieve them. Table 8-7 on page 298 shows how a rising edge interrupt would be configured for pin
2 of a GPIO port.
Table 8-6. GPIO Pad Configuration Examples
GPIO Register Bit Value
a
Configuration
SLRDR8RDR4RDR2RPDRPURDENODRDIRAFSEL
XXXX??1000Digital Input (GPIO)
??????1010Digital Output (GPIO)
????XX1110Open Drain Output
(GPIO)
????XX11X1Open Drain
Input/Output (I
2
C)
XXXX??10X1Digital Input (Timer
CCP)
XXXX??10X1Digital Input (QEI)
??????10X1Digital Output (PWM)
??????10X1Digital Output (Timer
PWM)
??????10X1Digital Input/Output
(SSI)
??????10X1Digital Input/Output
(UART)
XXXX000000Analog Input
(Comparator)
??????10X1Digital Output
(Comparator)
a. X=Ignored (don’t care bit)
?=Can be either 0 or 1, depending on the configuration
Table 8-7. GPIO Interrupt Configuration Example
Pin 2 Bit Value
a
Desired
Interrupt
Event
Trigger
Register
01234567
XX0XXXXX0=edge
1=level
GPIOIS
June 18, 2012298
Texas Instruments-Production Data
General-Purpose Input/Outputs (GPIOs)
NRND: Not recommended for new designs.