Datasheet

Table 8-5. GPIO Signals (108BGA) (continued)
DescriptionBuffer Type
a
Pin TypePin NumberPin Name
GPIO port C bit 0.TTLI/OA9PC0
GPIO port C bit 1.TTLI/OB9PC1
GPIO port C bit 2.TTLI/OB8PC2
GPIO port C bit 3.TTLI/OA10PC3
GPIO port C bit 4.TTLI/OL1PC4
GPIO port C bit 5.TTLI/OM1PC5
GPIO port C bit 6.TTLI/OM2PC6
GPIO port C bit 7.TTLI/OL2PC7
GPIO port D bit 0.TTLI/OG1PD0
GPIO port D bit 1.TTLI/OG2PD1
GPIO port D bit 2.TTLI/OH2PD2
GPIO port D bit 3.TTLI/OH1PD3
GPIO port D bit 4.TTLI/OE1PD4
GPIO port D bit 5.TTLI/OE2PD5
GPIO port D bit 6.TTLI/OF2PD6
GPIO port D bit 7.TTLI/OF1PD7
GPIO port E bit 0.TTLI/OA11PE0
GPIO port E bit 1.TTLI/OB12PE1
GPIO port E bit 2.TTLI/OB11PE2
GPIO port E bit 3.TTLI/OA12PE3
GPIO port F bit 0.TTLI/OM9PF0
GPIO port F bit 1.TTLI/OH12PF1
GPIO port F bit 2.TTLI/OJ11PF2
GPIO port F bit 3.TTLI/OJ12PF3
GPIO port G bit 0.TTLI/OK1PG0
GPIO port G bit 1.TTLI/OK2PG1
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
8.2 Functional Description
Important: All GPIO pins are tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0,
and GPIOPUR=0), with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]).
The JTAG/SWD pins default to their JTAG/SWD functionality (GPIOAFSEL=1,
GPIODEN=1 and GPIOPUR=1). A Power-On-Reset (POR) or asserting RST puts both
groups of pins back to their default state.
While debugging systems where PB7 is being used as a GPIO, care must be taken to
ensure that a low value is not applied to the pin when the part is reset. Because PB7
reverts to the TRST function after reset, a Low value on the pin causes the JTAG
controller to be reset, resulting in a loss of JTAG communication.
Each GPIO port is a separate hardware instantiation of the same physical block (see Figure
8-1 on page 295). The LM3S8962 microcontroller contains seven ports and thus seven of these
physical GPIO blocks.
June 18, 2012294
Texas Instruments-Production Data
General-Purpose Input/Outputs (GPIOs)
NRND: Not recommended for new designs.