Datasheet

Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0,
GPIODEN=0, GPIOPDR=0, GPIOPUR=0, and GPIOPCTL=0, with the exception of the
four JTAG/SWD pins (shown in the table below). A Power-On-Reset (POR) or asserting
RST puts the pins back to their default state.
Table 8-1. GPIO Pins With Non-Zero Reset Values
GPIOPCTLGPIOPURGPIOPDRGPIODENGPIOAFSELDefault StateGPIO Pins
0x10011UART0PA[1:0]
0x10011SSI0PA[5:2]
0x10011I
2
C0PB[3:2]
0x31011JTAG/SWDPC[3:0]
Table 8-2. GPIO Pins and Alternate Functions (100LQFP)
Multiplexed FunctionMultiplexed FunctionPin NumberIO
U0Rx26PA0
U0Tx27PA1
SSI0Clk28PA2
SSI0Fss29PA3
SSI0Rx30PA4
SSI0Tx31PA5
CCP134PA6
35PA7
PWM266PB0
PWM367PB1
I2C0SCL70PB2
I2C0SDA71PB3
C0-92PB4
C0o91PB5
C0+90PB6
TRST89PB7
SWCLKTCK80PC0
SWDIOTMS79PC1
TDI78PC2
SWOTDO77PC3
PhA025PC4
24PC5
PhB023PC6
22PC7
CAN0Rx10PD0
CAN0Tx11PD1
U1Rx12PD2
U1Tx13PD3
CCP095PD4
June 18, 2012290
Texas Instruments-Production Data
General-Purpose Input/Outputs (GPIOs)
NRND: Not recommended for new designs.